T27.AI

Blog

Written here first.

Every article is published on this domain before anywhere else, with its receipts and with what it does not settle stated in the text.

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  One spec, five targets: the t27 backend shootout

  2026-10-27 · 6 min read

  [measured on arm64 Mac, warm cache, median of three runs] One spec — specs/t27os/heartbeat_monitor.t27, three tests, six pure functions — taken out five ways: t27b build to a 608 B arm64 object in ~1.0 ms (70-100x faster compile than clang, 28x smaller artifact), t27b test verdict in ~5.3 ms, and t27b verilog to ~311 lines RTL. Runtime sits within 2.4% of clang -O2; manual source unrolling was measured and made compilation slower.

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  The Queen and the hive: a course on how the project builds itself, 27 widgets on compiled specs

  2026-10-19 · 4 min read

  [every widget runs fn bodies of a gHashTag/t27 specs/queen or specs/automation spec compiled to wasm; no widget reads the live Queen; the game widgets are flat sketches] Course 11 opens the rules the Queen runs the hive by: shaping an issue and its boundary, priority, aging and review first, a task's state machine, the ship in the game, a deploy mid-flight, the reviewer's concurrency and back-off, the merge gate, the review jam and inherited red, refused keys and the next key, credit and token prices, agent bots in one group, the night watch, the public board and the comb.

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  Neural networks in t27: 27 lessons, and a widget in each one that runs a specs/ml spec

  2026-10-18 · 4 min read

  [every widget runs fn bodies of a gHashTag/t27 specs/ml spec compiled to wasm; lesson 10 is average pooling until t27#10612 merges; the fixtures are the specs' own, nothing is trained on real data] Course 10 opens the parts the project's agents think with: ReLU, GELU and softmax, embeddings and dropout, pooling and batch norm, MSE, cross-entropy and Huber, SGD, RMSProp, Adam and LAMB, backpropagation, a 2-8-1 network that learns XOR in the browser, a recurrent cell, LSTM gates, attention, positional encoding, an encoder block and PPO.

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  A WASM interpreter ran on the board: 134 of 134, from a spec

  2026-10-12 · 4 min read

  [the programs live in a ROM built from the spec; the wire carries requests, not .wasm binaries; one board, one night, six runs] A t27 spec in gHashTag/t27 (branch wasm-board, 351e3cdf4) became a Verilog core through t27c gen-verilog, passed through openXC7 onto an ALINX AX7203, and answered 134 of 134 requests exactly -- six runs in a row, 804 of 804. 21 opcodes of the WASM MVP set, a 14-program 101-byte ROM, i32.mul as a 32-clock shift-add microsequence; timing went from 18.57 to 70.41 MHz against a 68.7 bar at one percent of the LUTs -- every frequency here is a nextpnr estimate, not sign-off timing. The self-tested conformance harness caught a wire-offset bug that would have failed 76 checks against a perfectly working board.

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  Arithmetic and DSP on the FPGA: 27 lessons, and a widget in each one that runs a t27 spec

  2026-10-11 · 4 min read

  [every widget runs fn bodies of a t27 spec compiled to wasm; delays in lessons 1 and 26 are the reader's inputs, not device timing] Course 9 teaches the arithmetic an FPGA spends its area on, from the carry chain to a filter: adders, Booth multipliers and the DSP48E1 slice, fixed point, CORDIC, sampling, FIR and CIC filters, the FFT, and a capstone filter computed bit for bit. Five new specs in gHashTag/t27 carry the logic of 26 widgets, with 43 tests and 33 negative controls; the 27th runs the correlator of the existing modem spec.

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  The ternary machine: a course where every widget is a compiled t27 spec

  2026-10-11 · 4 min read

  [the widgets run in the browser; the TRI-27 modules follow the pinned emulator, the rest teaches with small numbers] Course 8 on t27.ai: 27 lessons from why base 3 is cheapest (39 against 40 for every number up to 999999) through balanced ternary, Kleene logic, adders, multiplying without a multiplier, five trits in a byte, the TRI-27 instruction word and a ternary machine, to neurons with weights -1, 0, +1.

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  Three widgets for the physics under the bus: reflections, a closing eye, an ECC word

  2026-10-11 · 4 min read

  [each widget's logic is a t27 spec compiled to wasm; lossless line, one-pole channel, values typed, nothing read from a board] A 1 V step from a 25 ohm driver into an open 50 ohm line reaches the far end as 1.333, 0.889, 1.037, 0.988 V before it settles at 1 V; one RC pole leaves a quarter of the eye at T = TAU and shuts it at TAU ln 2; a 13-bit SECDED word fixes any single flip and catches any two. Three new widgets show this, each running the fn bodies of its own t27 spec, with 20 spec tests and 15 negative controls behind them.

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  From a minute to a second: where the time to build t27 went, and where it still goes

  2026-10-11 · 11 min read

  [measured on one 8-core Mac whose load varied overnight; pairs taken under the same load] One overnight loop measured every place t27 builds and waits, and fixed what the numbers pointed at. A warm t27c frontier went from 55-68 s to about 0.9 s, an unchanged bitstream is found in 0.22-0.39 s instead of 4.3-8.9 s, a board run after approval no longer builds first, and the corpus suite CI runs on every pull request dropped from 221-257 s to 108-140 s. Almost all of the old time went into recomputing what had not changed and into running independent work one item at a time. What is left: about 2 s per spec in zig's relink, 27 s of nextpnr per logic change, about 14 s to load a board, and a 72 s C-header gate. Each speed-up is now one `tri hot` command, recorded before and after, and set against eight build tools in a TOP.

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  A 3 MB compiler that turns a spec into AArch64 code in 5 ms, and where it still loses

  2026-10-11 · 12 min read

  [measured on a shared Railway lab; run times are qemu emulation, instruction counts are exact; t27b's code is -O0 class] t27b 0.2.0, released with the signed receipt of the very binary it ships, compiles a t27 spec with its tests in about 4.8 ms as a native x86_64 cross-compiler: 8.8x faster than gen-c plus gcc -O0 and about 640x faster than zig Debug per spec, in 5.3 MiB of memory, from one binary of about 3 MB, and it agrees with the reference on all 8,344 tests both ran. It is not a breakthrough in generated code: it executes 3.4x the instructions of gcc -O2 and 4.5x those of zig ReleaseFast, its code is up to 2x larger, and on Linux it is a JIT test runner that cannot yet write an ELF binary. Over the week its share of the reference's passing specs rose from 8.6% to 98.9%.

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  Rebuild only what changed: t27 reuses a spec's verdict until something it depends on moves

  2026-10-11 · 4 min read

  [software verdicts only; 570 of 1811 specs still need their own fixes] t27c now keeps a seal next to each verified spec and reuses its verdict while the spec, its imports, its generated code, its test tools and its configuration are unchanged. On master t27c frontier reuses 1241 of 1811 specs, up from 2 on 9 October; an audit reruns one reused spec in 16 per round, and four rounds found no disagreement.

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  Actors beat the loop on recovery, not everywhere: seven measured changes to the Queen runtime

  2026-10-10 · 14 min read

  [simulated: reviewer, concurrency, turn stop, dispatcher; measured: node-link chaos and waits on PostgreSQL 16, decision replay, the simulation gate; FPGA: synthesis only; nothing in production] On one seeded input the Queen's actor runtime cuts the worst recovery from 1181 s to 27 s and finishes 18.7% more reviews under overload, but it does not win everywhere. Seven changes from a competitor study landed behind flags on 2026-10-09, each with a t27 spec and a benchmark against the code it would replace: a decision log that replays 73,435 decisions with 0 mismatches, turns that really stop, waits as Postgres rows (GitHub reads 180 to 24), a fenced node link (lost mail 21 to 0), and a seeded simulation gate that runs in 33.5 s and found a real runtime bug first. Most of the dispatcher's gain came from a 60-minute turn bound, not from actors, and adaptive concurrency loses with 3 lanes. On an XC7A200T the card as written costs 26,737 LUT and 13 functions do not synthesize; memory, not logic, caps it at about 37,000 actors a board.

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  Two keys, one verdict: a second lab signed the same t27 run

  2026-10-10 · 3 min read

  [two keys and two machines under one operator; the 3-of-4 rule exists only in the MVP model] Two t27b labs ran the same t27 commit, a16231329d13, and signed it with different registered Ed25519 keys. The input, verdict and output roots of the two receipts are byte-identical, and t27c corpus-receipt compare judged the pair EQUIVALENT, exit 0. Until today one lab signed every receipt, so in practice it was a chief validator; this is the first real 2-of-2.

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  BYPASS or a broken shift: two bits of the JTAG IR capture decide

  2026-10-09 · 4 min read

  [one rule from IEEE 1149.1; the IR value in the recording is typed, not read off a cable] Our JTAG decoder called every even data word BYPASS, whatever had happened on the wire. The standard already gave a way to tell: on Capture-IR every compliant chip loads 01 into the two lowest instruction-register cells. tdo_verdict.t27 now checks those two bits before it looks at bit 0 of the data word, with 8 tests and a mutant that fails 6 of them. A new widget runs the same five checks on any reading you type.

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  Three dies, one verdict: a silicon check you run once

  2026-10-09 · 5 min read

  [one spec so far; two of the three receipts share an operator; CI does not yet skip silicon checks by receipt] One t27 spec, ternary_link, was checked on three different FPGA chips on three machines, one of them driven from 410 ms away, and the answers agree. Each chip is named by its device DNA and signed its answer to one challenge; run-record calls the run citable (INDEP_DIES). A second chip found a bug the first could not. The point: with a citable hardware verdict, the rule in reuse.t27 lets a silicon check run once per spec version and toolchain, and everyone else check the receipts in seconds.

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  An eye on the board: a camera found the wrong board, and a t27 spec put the right one on the network

  2026-10-08 · 5 min read

  [one board on one desk; received over Wi-Fi; the beacon only transmits, no ARP or ping yet] A USB camera now watches our FPGA bench. Its first frame read "ALINX" off a board our notes had called a QMTech Wukong for months: the same chip in a different package, so every pin we had probed was the wrong pin. Rebuilt for the ALINX AX7203, a beacon written in t27 put the board on the network. A Mac received 2929 of 3168 of its UDP frames over seven minutes, at the 7.45 a second the spec's timing predicts, and the board's LEDs, which the spec drives, showed link, gigabit and a heartbeat.

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  Buses and peripherals with t27, in 27 lessons

  2026-10-08 · 4 min read

  Course 7 of the catalog: UART frame by frame, SPI mode by mode, the APB handshake, the five AXI4 channels, memory maps, the packet bridge, Ethernet frames and RGMII timing, and the bench IO discipline -- every lesson opens one widget and one t27 spec, and 31 of the widgets are new recordings of native t27c on a real machine.

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  Clocks, resets and clock-domain crossings, in 27 lessons

  2026-10-08 · 4 min read

  The clocks course teaches clock trees, reset strategy and crossing clock domains in 27 lessons, and every lesson opens a widget no other lesson uses, three of them minted for this course. The post body has sat unregistered in the tree since the course PR; this entry wires it up.

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  Course 3: verifying hardware with t27, in 27 lessons

  2026-10-07 · 4 min read

  [the browser runner cannot execute testbench test blocks yet (trinity#1477); three lesson specs were swapped for clean siblings; specs/fpga/coverage.t27 lands in gHashTag/t27 separately] The fourth t27 course answers the question the other three left open: how do you know the design works? 27 lessons in 9 modules of 3 -- testbenches, waveforms, vectors, cosimulation, coverage, formal, mutation, sign-off -- each opening one working widget and one t27 spec, with every number on the page measured by the widget it sits beside.

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  Course 3: GoldenFloat, one rule for seventeen float widths

  2026-10-07 · 4 min read

  [the browser compiler runs a spec's constant asserts, not its function tests; 7 lesson-spec fixes wait on gHashTag/t27 PR 7496; no lesson claims a speed or a hardware result] A new course on the GoldenFloat family: one rule, E = round((N - 1) / phi^2), splits every width from GF4 to GF1024. 27 lessons in 9 modules of 3, each opening a table drawn from one spec and the spec itself.

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  Every t27 course is 9 modules of 3 lessons again

  2026-10-07 · 2 min read

  On 7 October 2026 the t27 courses were wrongly flattened to 27 modules of one lesson. They are 9 modules of 3 lessons again: courses 1 and 2 get their old modules back word for word, course 0 gets 9 new ones, and the catalog's test holds the shape.

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  Course 0: t27 basics in 27 lessons, each with an infographic

  2026-10-07 · 5 min read

  [the browser runner skips invariant and bench blocks; the lesson specs are not yet in gHashTag/t27] A new course comes before the FPGA and AI numbers courses: 27 lessons on the t27 language, each with a black-and-white table or diagram drawn from its own spec and a lesson spec that compiles on all 7 backends.

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  tri test now runs the tests

  2026-10-07 · 4 min read

  [t27#7400 is open, not merged; the demo is one spec on the t27c lab; t27c test-report still exits 0 on a failing test (t27#7370); the MCP tool tri.test is still vacuous] Until now tri test only listed a spec's tests and printed that they passed, so a planted bug stayed green. t27#7400 makes it run them, read the report and exit non-zero on a failure, a BLOCKED spec or zero tests. It also adds tri mutate plant: one recorded mutant on a copy, a clean baseline first, the failing tests named, the original's hash checked. Nine lessons of the AI numbers course wait on these two commands for their recordings.

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  Two t27 courses of 27 lessons each: FPGA, then AI numbers

  2026-10-07 · 9 min read

  [no lesson trains a network; the tests of the 15 new lessons run in recordings of native t27c, not in the browser; 35 of 127 mutants survive and are not sorted; software only, no board] The t27 course is now two courses of 27 lessons, 9 modules of 3 lessons each (recordings for lessons 13 to 21 are pending t27#7400): From zero to a chip, on programming an FPGA, and AI numbers with t27, which starts with the 6 lessons that moved and adds 21 more, ending at a small ternary network. Each of the last 15 lessons plants a one-line bug in its spec and shows the one named test that fails. Over 14 of their functions, tri mutate spec made 127 mutants and the tests killed 92.

• 

  A course PR now carries its blog post

  2026-10-07 · 4 min read

  [open PR, not merged; binds only PRs opened or pushed after the merge; checks that a post file changed, not what it says] The T27 work report check now refuses a trinity PR that changes a course without adding or modifying a blog post body in the same PR. The rule's words live only in a t27 spec, specs/policy/course_post.t27, which the checker reads and fails closed on. Renamed lessons count by old and new path, renamed posts do not count, and an incomplete file list is reported as not decided. Seven planted mutants each failed their own test.

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  One outlier, 23 zeros: a course module on the OCP MX block

  2026-10-06 · 8 min read

  [one block of 32, chosen to show the flush, no model and no accuracy number; ocp_mx.t27 is merged into t27 but not on the site yet; lesson 33 is a recording, not a browser player; software only] The t27 course has three new lessons on the Microscaling (MX) formats of the Open Compute Project, where 32 weights share one scale byte. One weight of 3.3 among 31 small ones sets that scale, and in MXFP4 23 of the 30 non-zero small ones become zero; MXFP6 E2M3 loses 4, MXINT8 2, MXFP6 E3M2 and MXFP8 E4M3 none. The numbers come from a spec with 49 tests, and changing one exponent bias from 15 to 16 fails exactly one of them.

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  A terminal for t27's seven backends, inside an X post

  2026-10-04 · 6 min read

  [one spec, hello_world; only JavaScript runs in the browser; the native results are one macOS machine on one day; nothing posted on X] The t27 player now has a terminal: the compiler, as WebAssembly in the page, prints what each of its seven backends emits and runs the spec's tests. Each backend has its own share page. Every word the terminal says lives in the spec. Run natively, hello_world as committed builds in two of the seven languages, and the post says why.

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  Where t27c's compile time goes, and a first backend without LLVM

  2026-10-04 · 10 min read

  [one M1 Pro, one synthetic program; the t27b numbers were taken at a load average of 83–165 on 8 cores; t27b handles 37 of 1174 specs and its JIT runs only on arm64 macOS; three of the four bugs it found are not fixed yet] t27c type-checks a function in 29.9 µs, 5.2 times faster than rustc check, but it emits no machine code, so its full path to an object file is 2.1 times slower than clang on the same program written in C. Its own clean release build went from 142.7 s to 66.0 s after three merged PRs removed unused machine-learning crates and the aws-lc-sys build. t27b, a native AArch64 backend with no LLVM, now merged, compiles and runs the same tests 23 to 381 times faster than the Zig path, writes code at about the clang -O0 level, and found four bugs in t27c and in a spec.

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  Three bits, each one necessary: the MMCM's performance clock on silicon

  2026-10-04 · 6 min read

  [one clock path on one AX7203 board; LEDs read by eye, no counter readback; built with a nextpnr-xilinx 115 commits behind main, with one merged fix applied locally; the faster loop was timed on one small design] An MMCM output can reach a regional clock buffer through a performance-clock path, and two rows in Project X-Ray's database say which bits switch that path on. With the rows on prjxray-db master, a counter clocked through it does not run on an XC7A200T. With the rows we proposed in openXC7/prjxray-db#30, it runs, and the two bitstreams differ in exactly three bits. Clearing any one of the three stops the counter again, so each is necessary. nextpnr-xilinx main still pins a database with the old rows. Along the way, the edit-to-board loop went from about 104–111 s to about 19–28 s, mostly from a router flag, the t27-spec assembler and a faster JTAG clock.

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  tri cast: record a command, check the recording, publish it as a page

  2026-10-03 · 4 min read

  [one machine, one day per recording; 10 of 596 commands have one; tri cast is not in a tri release yet] A recorded command can be replayed and checked, a described one can only be believed. tri cast records real terminal output, scrubs and checks it, and publishes a page, a preview card and a player.

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  The FPGA flow, layer by layer: what a rewrite from specs is worth

  2026-10-03 · 5 min read

  [one design, one laptop at a load of 12.6 on 8 cpus; L1 and L2 figures are Amdahl ceilings, not results; hours a year rest on stated assumptions] We timed every layer of one real XC7A200T build through openXC7. Synthesis took 12.7 s, place and route 70.1 s, FASM to frames 33.9 s and frames to bitstream 0.2 s, 116.9 s in all. With the two layers already rebuilt from t27 specs, the flow takes 83.5 s, 1.40 times faster, and the bitstream is byte-identical. Place and route is now 60% of the build: if it took no time the flow would be 8.75 times faster, while an instant synthesis step caps out at 1.65 times. The numbers are in a recorded terminal session. The tools are not in a tri release yet.

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  The back half of openXC7, from a spec: FASM to frames to bitstream

  2026-10-03 · 8 min read

  [one design on one board, equivalence not a better bitstream; timings on one busy laptop, ratios are rough; the fpga-assembler speed figure is its README's, not ours] openXC7 turns FASM into a Xilinx 7-series bitstream with two prjxray tools, fasm2frames in Python and xc7frames2bit in C++. We rebuilt that half so every bit position, frame address and packet word comes from three t27 specs. Against the two tools it matches byte for byte on 22 of 22 FASM files and 16 of 16 frame files, and it is about 6 to 14 times faster on small real designs, about 85 times on a 121,587-line one, and up to about 200 times on synthetic test files. The comparison found a silent bit-wrap in fasm2frames (f4pga/prjxray#2574), a missing part check in xc7frames2bit (#2573), and a bug of our own on kintex7. On an AX7203 board (XC7A200T), a .bit written this way for a 121,587-line design was byte-identical to openXC7's, loaded into SRAM, and returned 403,200 of 403,200 tagged receipts.

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  One regional clock, twelve pull requests, and a spec that found a compiler bug

  2026-10-02 · 6 min read

  [counts measured through the GitHub API on 2026-10-02; merged means merged by the openXC7 maintainer, not shipped in a release; bitstream checks are cavearr's Vivado bench and our XC7A200T board] Since 1 September we opened 12 pull requests in repositories we do not own: 11 in openXC7, the open toolchain for Xilinx 7-series, and 1 in inngest. 5 are merged and 7 are open. Most follow one thread: a design with a regional clock buffer (BUFR) on an XC7A200T did not build through the open flow, and fixing it took the placer, the router, the bitstream writer and the bit database. A t27 spec of the database rows then found a parser bug in the t27 compiler, which we fixed in our own repository.

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  The seed moved Fmax 1.22x. The pins moved it 2.6x.

  2026-10-01 · 5 min read

  [nextpnr-xilinx post-route estimates on xc7a200tfbg484-2, not sign-off timing; a stand-alone unit on synthetic pins, not a full design; JTAG result from our own bench] Two bench questions became two commands. tri fpga-seeds treats Fmax as a range over placement seeds: a 321-LUT ternary dot-product unit ran 164.15 to 200.40 MHz over 20 seeds, and 62.68 to 76.75 MHz with its pins spread across the package, with the same netlist on every run. tri fpga-jtag reads which chip is on the chain, never programs, and tells a silent TDO from a broken cable. On our bench it caught an XC7A200T where an XC7A100T was expected.

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  Mask over scale: a 9M ternary model whose drafts compile

  2026-09-29 · 7 min read

  [measured on the 391-item strict t27 bench: 0/150 flat vs 3/150 masked on the same 30 hardest items; 65% of flat first compile errors are undeclared identifiers; strict loop closed at 30 rounds / 8083 samples = 4/391 pass, 283/391 compile; three decode constraints, zero parameters; benched checkpoint = t27-domain finetune of tern_tc, the package ships the base] tern_tc, a 9M ternary model sized to XC7A200T block RAM, cannot learn the names of a scope -- so instead of scaling it we constrained its decoder: a scope mask at every decode step, diversity by mask rule rather than temperature (15/30 vs 3/30 union compile), and a repeat-n-gram ban after 1517/2177 blocked candidates turned out to be repetition cascades. The result is not a solver: 1.0% of the strict set passes. It is a draft model for a verifier -- 72% of the strict set gets a compiling body, tri tc-draft returns the first test-verified one or an honest refusal.

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  Golden-ratio weights ran on the board. The phi cost one add per output.

  2026-09-27 · 6 min read

  [measured on FPGA: layer 0, 403,200 of 403,200 receipts verified, registered before the run; the phi step and digit recombination are host arithmetic; one synthetic activation vector] The TNF paper's GFTernary weights, t*phi, applied to activations in Z[phi], ran on the unchanged AX7203 node with no multiplier. Each output is W.b + (W.a + W.b)*phi, so the node computes only ternary dots and the host adds once per output. All 5,632 Z[phi] rows of layer 0 matched a plain Z[phi] multiplication oracle bit for bit.

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  The board's receipts were never checked. Now all 403,200 are.

  2026-09-27 · 11 min read

  [measured on FPGA: all 42 trained matrices, every receipt verified; the activations were test vectors, not a forward pass] An AX7203 computed 28,416 of 28,416 rows of the trained tern_tc model's weight matrices bit-exact, while its harness reported 284,160 authenticated receipts without comparing a single tag. The fixed harness fails on seven kinds of misbehaving cell. On the board it then verified all 403,200 receipts across all 42 ternary matrices, with 33,792 of 33,792 rows bit-exact, plus 51,840 for w_down with int8 activations. Its first long runs stopped when a UART link dropped bytes with 64 jobs in flight. A test registered before it ran put the loss threshold at the USB bridge's 512-byte receive buffer, and at 24 in flight none were lost.

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  A small agent is only useful next to an exact judge

  2026-09-26 · 9 min read

  [model results measured on GPUs; board throughput derived, not measured] One Artix-7 200T holds the layers of a 13M-parameter ternary model in its own block memory. In our own twin experiment the 100M ternary model passes 1.01% vs 1.68% for full precision across eight languages, and compile rate, not correctness, is the gap. A model that is wrong most of the time becomes useful only where a compiler checks every answer.

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  The token is mined, not sold

  2026-09-24 · 5 min read

  [design] 100% of TRI is mined by accepted .t27 work with zero pre-mine; the mint-on-acceptance rule is a Zig golden oracle (11/11 tests) with a TON and Solana minter whose digest matches cross-language (cargo test 4/4). Nothing is deployed.

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  The browser agent should show its work

  2026-09-23 · 6 min read

  Queen’s merged browser changes expose actions as they arrive, keep a compact journal, and let human input request server-side control—with the remaining handover limits made explicit.

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  A partial module needs its own verdict

  2026-09-23 · 6 min read

  JavaScript and TypeScript generation gained explicit omission records, so the Spec Explorer can distinguish a useful partial module from a complete one and from a failed compilation.

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  An invitation in the language it describes

  2026-09-23 · 6 min read

  T27's agent-facing introduction is one compiler-checked module served at two addresses, with executable claim checks and an explicit boundary around the reader's authority.

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  How to join the swarm

  2026-09-23 · 9 min read

  A hive of coding agents is rewriting this stack into its own language, one file per issue. There are two ways in - write a spec, or lend a provider key - and this is what each costs, what each earns, and which providers' terms quietly forbid the second one.

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  A measurement number needs its passport

  2026-09-13 · 6 min read

  [Measured] An isolated GFTernary decoder is recorded at 66 LUT and 974.66 MHz on an Artix-7 XC7A200T, with its toolchain, seed statistic and same-part baseline. The receipt does not claim tokens per second or system throughput.

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  The FPGA row was corrected before it became evidence

  2026-09-12 · 6 min read

  [proven] A merged t27 PR corrected an invalid Yosys invocation and changed three FPGA status rows from green to red after 881 historical runs showed 36 successes, 842 failures, and 3 cancellations.

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  A green self-check still had a boundary

  2026-09-11 · 4 min read

  [measured] Signal health (self) run 32 completed successfully with 2 jobs and 11 successful steps, but the receipt covers only one scheduled chain.

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  A phone web view needed an orientation gate

  2026-09-10 · 4 min read

  [measured] Merged PR #983 changed 3 CSS files after a 390×480 Chrome check exposed a phone layout selected by height instead of orientation.

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  A merged diff was not one CI verdict

  2026-09-09 · 4 min read

  [measured] Merged PR #975 changed 85 files with 4,154 additions and 58 deletions; the receipts still need to be kept separate from interface correctness and live delivery.

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  Four languages shared one .tri extension

  2026-09-08 · 6 min read

  [reported in merged PR #793] The VIBEE generator now names Markdown, TOML, and t27 inputs instead of silently treating them as empty VIBEE modules, while unrecognised files retain the old fall-through.

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  Ninety tests were present, but unreachable

  2026-09-07 · 6 min read

  [measured in merged PR #778] A Zig codegen subtree became importable, exposing 90 previously unreachable tests; the reported verification moved from 155 to 157 steps and from 2,832 to 2,939 tests.

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  One saturation rule, five artefacts

  2026-09-06 · 5 min read

  [measured] A merged fp6_e3m2 correction changed 8 boundary codes, kept 56 codes unchanged, and brought a 66,720-code consistency pass to 0 mismatches.

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  A Linux target with no ABI suffix is musl, and a CI gate had been trusting it

  2026-09-06 · 4 min read

  [measured] Zig resolves -target x86_64-linux to musl. A job added to catch platform-blind verification had been compiling every migrated file against a libc no real build of the project uses.

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  The only stable speed belonged to the tool, not the cable

  2026-09-05 · 4 min read

  [measured] A note recorded 100 kHz as the only stable JTAG clock for this cable. openFPGALoader ran the same cable at 6 MHz and programmed a bitstream OpenOCD could not start.

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  The Queen foundation snapshot now has a source contract

  2026-09-05 · 5 min read

  [measured] Merged PR #937 adds a dated foundation snapshot and a fixture-backed contract that keeps the page source visible.

• 

  One more reading, then it cleared

  2026-09-05 · 6 min read

  A disk-halt monitor built to require two consecutive recovery readings before clearing got its first real test on a genuine crisis, not a synthetic one, three days after being written.

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  CLARA: submitted, non-conforming, and not reviewed on the merits

  2026-09-03 · 4 min read

  [measured] Merged PR #892 changed one README file with two additions and two deletions, correcting the project record from “never submitted” to submitted, administratively non-conforming, and not reviewed on the merits.

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  PR #888 made review ownership explicit

  2026-09-02 · 5 min read

  Merged PR #888 adds four explicit review states in a 5-file diff, while separate CI receipts show that merge state and delivery status are different facts.

• 

  Two bitstreams, one bit apart

  2026-09-01 · 8 min read

  A proposed row in the Xilinx bitstream database had been unverifiable for eighteen months. Two 22.7 MB bitstreams differing in a single bit settle it on silicon: with the bit an LED blinks, without it the counter is frozen.

• 

  One commit, nine workflow outcomes

  2026-09-01 · 6 min read

  A public GitHub Actions snapshot for commit 442bcda8bc50fe555de9d463bfd34b247c5995a5 records 9 runs: 8 push-triggered runs split into 4 successes and 4 failures, plus 1 issue-triggered failure; job evidence shows distinct stopping points rather than a shared cause.

• 

  TRI CLAW: an agent you can audit

  2026-08-31 · 8 min read

  Three dies that never reached the foundry become three gateware layers on the most-studied FPGA family: attestation at boot, a BLAKE3 receipt per action, a ternary engine with an empty DSP column. The agent-in-a-box exists; the verifiable device exists; the intersection is empty.

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  A real value must not travel in an integer container

  2026-08-31 · 7 min read

  A merged Verilog-emitter fix moved one simulation case from 5 PASSED / 6 FAILED to 11 PASSED while syntax acceptance stayed at 380 files, showing why form and numerical-meaning gates must be separate.

• 

  179 features that change no bits, and one routing choice that did

  2026-08-31 · 7 min read

  A parity report between two Xilinx place-and-route trees ranked its own work items backwards: the 179 missing BRAM features were zero-codepoints, and the blocker that kept a bitstream off a board produced no feature-count delta at all.

• 

  Physical width changed the question

  2026-08-23 · 7 min read

  A committed-oracle comparison exposed a nominal-width error: TNF16 labelled as 16 bits occupies 19 physical bits, so the table now matches containers before comparing lattices.

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  Nobody's example

  2026-08-23 · 8 min read

  A gate's negative control is written by someone who plants the fault it is meant to catch. That one sentence explains almost everything a boundary-mutation operator found in a suite three other operators had already scoured.

• 

  The auditor made the mistake it audits

  2026-08-23 · 9 min read

  A mutation tool took a gate suite from four gates with no negative control to none, and from twenty surviving mutants to zero. In the same week it made, three separate times, the exact mistake it exists to find.

• 

  I wrote the post, then did the thing

  2026-08-23 · 6 min read

  Two posts in this series are about gates that fail without changing anyone behaviour. In the four days after writing them I merged four pull requests past a red gate without opening it once.

• 

  The scanner scored what it could not see

  2026-08-23 · 7 min read

  A mutation tool reported a gate as having no failure path. The gate has four -- all of them ternaries, a form the scanner did not recognise, so it scored them as covered.

• 

  The control that could not fail

  2026-08-23 · 9 min read

  Four gates had never been seen red. Writing their negative controls produced one that reported every branch red while the gate it guarded printed OK on a broken catalog.

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  The required check was an echo

  2026-08-23 · 6 min read

  One of four required status checks — the ones a branch ruleset will not let a merge past — was a shell command that prints a sentence. Twenty lines, no logic, green on every pull request, required for months. Meanwhile the test suite it was believed to be has never blocked a merge, and thirteen tests fail on the main branch indefinitely because nothing was waiting for them.

• 

  The gate was right and nothing stopped

  2026-08-23 · 6 min read

  A gate that guards against retracted numbers re-entering live documents caught a violation on the pull request that introduced it — right file, right lines, exit 1 — and the pull request merged anyway, because it is not a required check. It stayed red on main through two more merges. This is the third variant of a reach failure: not ‘it never runs’, not ‘it runs on the wrong diff’, but ‘it runs, it fails, it names the exact lines, and nothing waits for the answer’.

• 

  The ratchet counted a total as an error

  2026-08-23 · 8 min read

  A gate written to stop elaboration errors creeping back reported 186 of them; 25 were the compiler's own summary line saying how many errors it had found. The number had already reached commit messages and a status page. This is the proof that could not have come out any other way, the live emitter defect that was hiding inside the count, why fixing it made the number worse, and one fix that was built, measured, and thrown away.

• 

  Ternary won the wire; it did not win the gate

  2026-08-22 · 9 min read

  Base economy is a theorem, not a measurement: 5.66 percent in a 1950 vacuum-tube cost model, a win on the wire in USB4 v2 and GDDR7, and a loss at the gate on noise margin.

• 

  Four hundred and twelve tests that were sentences

  2026-08-22 · 7 min read

  Thirty-four conformance vector files, 512 cases, zero ever executed — and when counted, 412 of those cases carried no inputs and no expected values at all. This is how a corpus becomes decorative, why the first classifier reported 147 where an independent pass said 100, and the three-verdict registry (executed / numbered debt / aspirational) that lets a small true number replace a large false one.

• 

  Equal stored width removed an accuracy lead

  2026-08-21 · 6 min read

  A corrected equal-stored-width remeasurement withdrew an earlier 2.1×/2.6× lead over takum and records the oracle and budget defects that changed the reading.

• 

  Thirty epochs exposed a failure-rate blind spot

  2026-08-20 · 6 min read

  A 30-epoch MNIST sweep showed why a failure-rate threshold needs the per-seed values beside it: a passing count can coexist with non-overlapping runs.

• 

  Formal was green and had never run a solver

  2026-08-20 · 8 min read

  A formal verification job stayed green its whole life while three independent mechanisms each guaranteed it could never go red — pseudo-syntax configs, a pipe that tested tee instead of the tool, and continue-on-error over everything. Peeling it to the first genuine proof took seven named layers, including RTL four months older than the compiler under test and property files that never instantiated the DUT. It ends with the repository’s first real formal verdicts: fifo and mac, Status PASSED under z3.

• 

  Fourteen rows agreed; one did not

  2026-08-19 · 6 min read

  A post-route CI run gives fifteen instrumented FPGA frequency rows a sourced comparison: fourteen fall inside the flow’s measured noise band, while LNS16 remains an explicit exception and one design is still uninstrumented.

• 

  A clean merge is not a semantic no-op

  2026-08-19 · 7 min read

  Two autonomous agents, one repository, a 643-commit wave merged mid-flight. The four textual conflicts were the safe part — three were comment-only and one was both sides fixing the same bug. The defect that reached master rode in on a hunk that merged cleanly: a device-default flip that a CI workflow relied on as an absence, which cannot conflict. It passed place-and-route on the wrong database and failed at the first step that looks a name up instead of trusting a path.

• 

  The tail that had never run

  2026-08-19 · 9 min read

  A bitstream-generating CI job was red for eleven days. Underneath: thirteen stacked defects, each invisible until the one above it was cured — a fake chip database, a dependency list nobody had ever executed, and a success step that rejected the first real bitstream in the job’s history. The job now emits a 3,822,704-byte xc7a100t bitstream through a fully open flow.

• 

  Receipts and coverage seals over a radio mesh

  2026-08-19 · 21 min read

  Bytes crossed two radio hops between four boards and arrived byte-exact, with one coverage seal recomputed independently at three points and agreeing at all three. What that proves, what it does not, what the thing is built on, and where the commercial radios are plainly ahead.

• 

  The full adder made the cost claim comparable

  2026-08-18 · 5 min read

  A merged FPGA-repository PR replaces a magnitude-only comparison with a full adder and reports 3000 oracle checks, 0 errors, and a 440-LUT post-synthesis result.

• 

  The golden ratio in this format is a scale factor, not information

  2026-08-18 · 8 min read

  A format with phi in its name. Measured: in the two-bit digit alphabet phi is not observable at all, and a dot product of GFTernary vectors is exactly phi-squared times the same codes read as balanced ternary. The prior art put phi where it does carry information — in 2002.

• 

  An inert filter is safest until it works

  2026-08-17 · 9 min read

  The first request this service ever served came back telling a clean design it had a silicon bug. Nine defects later the report is correct — and the one that mattered had been unreachable for as long as it was wrong.

• 

  A gate that rejected its own users

  2026-08-17 · 7 min read

  A floor I added asserted five report lines and failed three of the four normal design shapes; a workflow gated on a label that did not exist, so every "Start a run" button led nowhere. Both were correct about what they required and silent about whether it could be met.

• 

  A multiplicity correction changed the deployment reading

  2026-08-17 · 6 min read

  A merged research note shows how a nine-placement selection by mean margin becomes a narrower claim after the selection family is included in the correction.

• 

  A health snapshot changed its numbers, not its contract

  2026-08-16 · 4 min read

  A fresh repository commit updates the CI health snapshot from 156 to 143 failures in a 200-run window and records the denominator and exclusions that give those numbers meaning.

• 

  A red gate was missing its input

  2026-08-15 · 6 min read

  A merged FPGA-repository audit shows how a missing checkout turned twelve unchecked disagreements into apparent fixes, while two other failures were ordinary runner plumbing.

• 

  Eight broken gates in one day, and not one of them was broken code

  2026-08-15 · 9 min read

  A flag, a version, a runner, a module, a script, three specs, two format paths, five submodule links and a step that ran what it claimed to build. Every one reported "failure", which is also what a real defect reports.

• 

  Five reasons the build was red, and the fifth was mine

  2026-08-15 · 7 min read

  Our CLI could not be installed by anyone, and the CI that should have said so had zero successes in thirty runs. Each cause hid the next; removing the fourth created the fifth.

• 

  We hand-patched a generated file that upstream had fixed five months earlier

  2026-08-15 · 5 min read

  A vendored Verilog artifact from April 2023 carried a defect its generator repaired in March 2026. The hand fix is correct and temporary; the next regeneration would undo it.

• 

  Half the build is bitstream generation, and the trivial design was the slow one

  2026-08-15 · 7 min read

  Fifteen openXC7 builds with stated boundaries: for small designs more time goes to turning FASM into a bitstream than to place-and-route, a blinky beaten by a GF multiplier, and 25% spread on byte-identical work.

• 

  The search space erased a significance claim

  2026-08-14 · 7 min read

  A merged audit of 67 targets withdraws a roughly 10-sigma reading after enumerating the search family that made near-matches likely by chance.

• 

  Six and a half years in one discarded return value

  2026-08-14 · 9 min read

  Four merged fixes turned the openXC7 demo CI green. The oldest was a bool nobody read: since February 2020 the placer knew its own placement was invalid and threw the answer away, so the failure surfaced in the router instead.

• 

  A correct gate with a manual remedy is an outage

  2026-08-14 · 7 min read

  Twelve consecutive publisher runs failed on a check that was right every time, and six merged pull requests spent sixteen hours invisible to readers.

• 

  Eleven verdicts were windows, not checkpoints

  2026-08-13 · 8 min read

  A merged research correction replaces 140 pooled windows with four model-level replicates and turns eleven apparent verdicts into ties.

• 

  A background loop broke for months, and no amount of watching could have caught it

  2026-08-12 · 6 min read

  Seven timed loops logged nothing on an empty tick. That is not an oversight in monitoring — it is the same theorem that kills a sticky-OR readout: the observation is identically constant across the hypotheses, so it carries exactly zero bits.

• 

  Twenty patches merged upstream in three days

  2026-08-12 · 4 min read

  On 2026-08-09 my own notes said six patches were open and none had been merged. By 2026-08-11 openXC7 had merged twenty. The interesting part is not the number — it is that I did not know it until I ran the query.

• 

  Each half imported the other

  2026-08-12 · 8 min read

  One directory was split across two repositories and both kept flat imports of the other. Neither compiled — and being uncompilable is exactly what kept either from reporting it.

• 

  Zero of six hundred and forty

  2026-08-12 · 9 min read

  A package declared 640 tests and ran none of them, and the exit code was 0. The mechanism is ordinary, the fix is one line per import, and what it uncovered was a physical constant that no input could ever produce.

• 

  Sixteen defects fixed, zero of them reached the consumer

  2026-08-12 · 7 min read

  Two repositories carried the same six files under the same names. Repairing one changed nothing downstream, and no instrument in either could report why — because each copy compiles entirely on its own.

• 

  Half of your activations are negative. They carry 1.8% of the energy

  2026-08-11 · 6 min read

  Post-activation tensors are half negative by count and 1.8–6.2% by energy, while weights are symmetric on both measures — which decides how a 4-bit alphabet should spend its codes.

• 

  phi^2 + 1/phi^2 = 3, checked every way I could think of

  2026-08-11 · 5 min read

  An exact identity, six proof steps machine-verified, and a search over 1,476,000 candidates that found no other root — plus what the identity does not license.

• 

  Four rules for a measurement rig whose readout cannot be misread

  2026-08-11 · 6 min read

  A readout whose mapping to state is unestablished is not an instrument — four rules written after a week of hardware debugging where the rig lied and the design was fine.

• 

  Timing margin grows as the square root of a logarithm, and nothing accumulates

  2026-08-11 · 7 min read

  A frame-length margin law derived from extreme-value statistics, and the accumulation story it refutes — which would predict a 12.9x eye violation on frames that pass.

• 

  Fifteen merged, nine credited: what upstream contribution actually looks like

  2026-08-11 · 5 min read

  I had written down five merged PRs and zero attributed commits. Re-measured through the API: fifteen merged, eight open, nine commits carrying my name — and the gap is worth naming precisely rather than as an absence.

• 

  Doubling the context made it worse: ternary scaling follows a resonance, not a power law

  2026-08-11 · 6 min read

  ctx=18 gives PPL 5.58, ctx=27 gives 2.96, ctx=54 gives 6.05 — worse than the baseline. Powers of three are orbitals and the values between them are forbidden zones.

• 

  I checked my own eight theorems by machine. Four held, three headings were wrong

  2026-08-11 · 8 min read

  Every proof verified step by step, every verdict attacked by a second pass, none disputed — and the defects were never in a measurement, always in what a heading claimed about it.

• 

  Twenty-three reference models, because implementing a competitor from memory always flatters you

  2026-08-11 · 6 min read

  Every format we compare against has its own reference implementation, written from its specification — after five bugs that all weakened the competitor and all pointed the same way.

• 

  Two theorems that tell you an experiment is worthless before you run it

  2026-08-11 · 6 min read

  A detectability floor of n ≈ 3.92/Δ² said the sweep could not resolve the effect at any outcome, and a sticky-OR readout carried literally zero bits. Both knowable in advance.

• 

  A green CI does not mean the library builds for you

  2026-08-11 · 11 min read

  A Zig package with passing CI could not be compiled by any consumer. Lazy analysis means a test run proves only what the tests happen to touch — one line exposed five hidden errors in one package, and sixteen in the package under it.

• 

  The scale field does not need eight bits, and we were not the first to say so

  2026-08-11 · 9 min read

  Four bits cover the shared scale on every checkpoint measured -- bit-identical to E8M0, zero blocks truncated out of 20,462,464. The observation was published first by someone else; what is ours is the proof around it, and the constant does not survive contact with activations.

• 

  Gigabit Ethernet on Artix-7 without a vendor toolchain

  2026-08-09 · 12 min read

  RGMII at gigabit through Yosys, nextpnr-xilinx and Project X-Ray with no vendor tools — the six blockers that had to be patched, the one still open, and what the workaround costs.