Verification service
Three tiers, and the button above starts the first one. They are separated because they establish different things: the free run is structural and concludes nothing about whether your design is correct, and saying so is the only way the other two mean anything.
Every node of your datapath checked against an independent reference model with known-answer vectors. Divergence between specification and RTL surfaces before synthesis, not after tape-out.
Achieved frequency, slack, LUT/FF/BRAM/DSP usage and a latch-free check — measured on a live Artix-7, not estimated from a report.
Bitstream, test vectors, logs and the exact toolchain versions, so anyone can re-run the whole flow themselves.
Yosys, nextpnr-xilinx, prjxray, openFPGALoader, iverilog. Nothing in the report depends on a proprietary licence you would need to buy.
And say what “correct” means for it.
Written from the operation, never from your RTL — a testbench derived from the same assumptions as a design agrees with the design's bugs.
Measured numbers, vectors, bitstream, and every command needed to reproduce it.
Turnaround: Minutes. Every file your info.yaml declares is present, and the design elaborates from that list alone.
Turnaround: 3–5 working days. A reference model written from your description of what the design should do — never from your RTL, because a model derived from the code agrees with the code including where it is wrong.
Turnaround: Days — board time is queued. Place-and-route on a named part, with the resource counters the router emits after routing completed.
Measurements come from a Xilinx Artix-7. This is not multi-corner characterisation and does not claim to be.
It is an independent check, not a substitute for a full commercial sign-off.
I verify what I can read. Encrypted IP cannot be checked this way.
Anything estimated rather than measured says so, here and in every report.
Have a design to verify? An introductory module is free, so you can judge the report before paying for anything.