Case studies
10 finished runs, 5 of them on designs that are not mine. Every check is shown with the command that produced it, and with what it does not establish. Produced on 2026-08-11 with: Yosys 0.65 (git sha1 aec814bdf3071f7e0fd0fbe43f7f711e99d01e24) · Icarus Verilog 13.0 (stable, v13_0). The workflow offered on this site pins a different build — a pinned oss-cad-suite release (2026-08-12), whose yosys build has been observed to vary — 0.68+71 and 0.68+80 on two runs of the same pin — so a re-run differs on cell count and agrees on wires and flip-flops.
Single-tile GF16 ternary dot4 MAC with a Lucas power-on self test. Top: tt_um_trinity_nano. Tiles: 1x1. Run of 2026-08-11.
16 of 16 declared files found in src/ (13 before the fix) Command: info.yaml source_files -> src/
clean, after the three missing files were declared Command: iverilog -g2012 -t null -I src -s tt_um_trinity_nano src/*.v
no $_DLATCH_ cells after techmap Command: yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*
10,534 cells including submodules, 4,050 wires. 4,663x $_MUX_, 2,252x $_AND_, 1,660x $_OR_, 1,316x $_XOR_ Command: yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat
210 flip-flops, so a clock frequency is a meaningful thing to ask about Command: yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist
GF16 e-engine, 8x2 tiles. Top: tt_um_ghtag_trinity_gf16. Tiles: 8x2. Run of 2026-08-11.
34 of 34 declared files found in src/ Command: info.yaml source_files -> src/
clean from the declared list alone Command: iverilog -g2012 -t null -I src -s tt_um_ghtag_trinity_gf16 src/*.v
no $_DLATCH_ cells after techmap Command: yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*
39,991 cells including submodules, 37,170 wires. 18,083x $_MUX_, 8,073x $_AND_, 5,823x $_OR_, 5,469x $_XOR_ Command: yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat
473 flip-flops Command: yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist
32-tile, 8-column neuromorphic array. Top: tt_um_trinity_max_true. Tiles: 8x4. Run of 2026-08-11.
44 of 44 declared files found in src/ (43 before the fix) Command: info.yaml source_files -> src/
clean, after the missing file was declared Command: iverilog -g2012 -t null -I src -s tt_um_trinity_max_true src/*.v
no $_DLATCH_ cells after techmap Command: yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*
205,992 cells including submodules, 102,588 wires. 90,628x $_MUX_, 45,141x $_AND_, 32,355x $_OR_, 27,239x $_XOR_ Command: yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat
1,929 flip-flops Command: yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist
Single-column cortex: 4 GF16 cells, 75-word ROM, 16-opcode ISA. Top: tt_um_qbrain_mini. Tiles: 1x1. Run of 2026-08-11.
1 of 1 declared file found (info.yaml declared none until 11 Aug 2026) Command: glob src/*.v
clean Command: iverilog -g2012 -t null -I src -s tt_um_qbrain_mini src/tt_um_qbrain_mini.v
no $_DLATCH_ cells after techmap Command: yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*
49 cells including submodules, 57 wires. 28x $_XOR_, 16x $_DFFE_PN0P_, 1x $_DFF_PN0_ Command: yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat
17 flip-flops Command: yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist
Holographic variant of the Quantum Brain column. Top: tt_um_qbrain_holo. Tiles: 1x2. Run of 2026-08-11.
1 of 1 declared file found (info.yaml declared none until 11 Aug 2026) Command: glob src/*.v
clean Command: iverilog -g2012 -t null -I src -s tt_um_qbrain_holo src/tt_um_qbrain_holo.v
no $_DLATCH_ cells after techmap Command: yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*
128 cells including submodules, 193 wires. 63x $_DFFE_PN0P_, 42x $_XOR_, 3x $_DFF_PN0_ Command: yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat
66 flip-flops Command: yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist
Somebody else's GPU, the largest of the three. Top: tt_um_pongsagon_tinygpu_v2. Tiles: see info.yaml. Run of 2026-08-11.
10 of 10 declared files found Command: info.yaml source_files -> src/
clean from the declared list alone Command: iverilog -g2012 -t null -I src -s <top> <declared sources>
no $_DLATCH_ cells after techmap Command: yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*
34,223 cells including submodules, 15,846 wires. 11,251x $_AND_, 9,213x $_OR_, 5,942x $_MUX_, 3,065x $_XOR_ Command: yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat
3,383 flip-flops Command: yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist
A floating-point synthesiser — the closest of the three to my own subject. Top: tt_um_float_synth_nikleberg. Tiles: see info.yaml. Run of 2026-08-11.
2 of 2 declared files found Command: info.yaml source_files -> src/
clean from the declared list alone Command: iverilog -g2012 -t null -I src -s <top> <declared sources>
no $_DLATCH_ cells after techmap Command: yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*
900 cells including submodules, 904 wires. 210x $_NOT_, 197x $_OR_, 180x $_AND_, 180x $_DFF_P_ Command: yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat
183 flip-flops Command: yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist
A bit-serial RISC-V core with a Wishbone SoC around it, across 40 declared files. Top: tt_um_divadnauj_GB_serv_soc_wb. Tiles: see info.yaml. Run of 2026-08-11.
40 of 40 declared files found Command: info.yaml source_files -> src/
clean from the declared list alone Command: iverilog -g2012 -t null -I src -s <top> <declared sources>
no $_DLATCH_ cells after techmap Command: yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*
8,301 cells including submodules, 4,903 wires. 2,081x $_AND_, 1,957x $_OR_, 1,605x $_MUX_, 689x $_DFFE_PP0P_ Command: yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat
1,751 flip-flops Command: yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist
A stochastic-computing neuron. Top: tt_um_santhosh_stoch_neuron. Tiles: see info.yaml. Run of 2026-08-11.
2 of 2 declared files found Command: info.yaml source_files -> src/
clean from the declared list alone Command: iverilog -g2012 -t null -I src -s <top> <declared sources>
no $_DLATCH_ cells after techmap Command: yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*
1,575 cells including submodules, 810 wires. 445x $_AND_, 439x $_OR_, 249x $_MUX_, 173x $_DFFE_PN0P_ Command: yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat
208 flip-flops Command: yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist
A serialiser/deserialiser, the smallest of the five. Top: tt_um_serdes. Tiles: see info.yaml. Run of 2026-08-11.
2 of 2 declared files found Command: info.yaml source_files -> src/
clean from the declared list alone Command: iverilog -g2012 -t null -I src -s <top> <declared sources>
no $_DLATCH_ cells after techmap Command: yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*
244 cells including submodules, 115 wires. 123x $_MUX_, 36x $_DFFE_PN0P_, 29x $_DFFE_PP_, 18x $_DFFE_PN0N_ Command: yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat
103 flip-flops Command: yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist
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