Measured evidence
Hardware claims are cheap to make and hard to check, so this page collects the results behind everything else: what was built, what it measured, and how it was verified. Where something is a submission rather than a win, or a prototype rather than a product, it says so.
A 4×4 matrix multiplier over my own GF16 format, synthesised for Artix-7. It maps into fabric with no DSP48 blocks at all, or 21,223 LUTs if the 64 hard multipliers are allowed. The block is combinational — no registers, so no clock and no frequency figure belongs to it.
Forward pass, gradient and weight update all in RTL with no host in the loop. A 2-layer ReLU network learns XOR on the chip itself, 4 of 4 correct, every node bit-exact from specification to the binary FPGA.
The design was submitted for fabrication through an open ASIC process: GDS was produced, the gate-level test passed, and precheck passed. No die measurements are claimed.
A float whose exponent is a balanced-ternary number and whose fields are fixed: no regime decode to pay for, and on a ternary fabric the exponent add is native. The accuracy lead over takum once reported here is withdrawn — at equal stored width the comparison ties rather than wins. What survives is measured in hardware, not accuracy: 38× fewer LUT on a full adder against a true base-3 opponent. Range is bounded at ±40 in powers of two; that limit is stated with every result.
133 formal specifications: GF16 physical layer, BPSK modem on AD9361, ETX mesh routing, ChaCha20-Poly1305 / X25519 crypto. Text and images carried between physically separate boards.
Bit-exact test vectors for FP8, BF16, MXFP4 and microscaling formats: a vendor-neutral reference for verifying low-precision arithmetic.
The reference model is written from the specification, never from the RTL.
Known-answer vectors at every pipeline stage, so a regression points at the stage that broke.
The same vectors run again on the physical board. Simulation agreement does not prove agreement on the binary FPGA.
Yosys, nextpnr-xilinx, prjxray, openFPGALoader, iverilog. No proprietary licence stands between a claim here and someone reproducing it.
A DARPA CLARA submission and an OpenAI Parameter Golf entry are submitted work, not awarded contracts or won prizes.
Measurements come from a Xilinx Artix-7 and are not multi-corner characterisation.
The on-chip training result is proven at small scale: a real network learning on a binary FPGA, not a production training accelerator.
Anything estimated rather than measured is labelled as estimated.
This page previously reported 323 MHz and 41.2 GOPS for the GF16 matmul. Re-checking the RTL on 8 August 2026 showed the block holds no registers, so it has no clock and no frequency can belong to it. Withdrawn rather than explained away.
The papers, the source and a full example report are all public. A claim you cannot verify is just a sentence.