Course
Not inference — training, on the chip itself. Eight modules from an empty toolchain to a network that learns on a binary FPGA, entirely on open tools: no Vivado, no licences, and no step you cannot reproduce yourself.
Yosys, nextpnr-xilinx, prjxray, openFPGALoader and iverilog installed and verified on macOS arm64 or Linux. A bitstream blinks an LED on a real board, no vendor licence anywhere in the chain.
Synchronous design, registers versus latches, and why an accidental latch is the classic bug that shows up on hardware.
Why float is expensive, what quantisation really costs, and where ternary and low-precision formats come from.
An independent Python reference model, per-stage known-answer vectors, checked through iverilog. Why a testbench written from the design's own assumptions cheerfully agrees with its bugs.
MAC to array to pipeline. Reading the router's timing report and fighting for frequency on a real example — including why a hard multiplier in the path can leave you with no frequency report at all.
Layers, activations, dataflow and on-chip memory, running on the board rather than in a simulator.
Backward pass and SGD in RTL. The network learns XOR on the FPGA itself, 4 of 4, bit-exact against the reference. Almost nobody has done this by hand.
The Tiny Tapeout path: preparing a design, what changes between FPGA and ASIC, and where the open ASIC ecosystem stands after the move to IHP.
Inference is generated through HLS and the flow underneath is a vendor toolchain. It does not train on the chip or leave you able to read the RTL it produced.
Built to teach you their tools on their hardware. Nothing transfers to a flow you can run without a licence.
Usually stop at simulation, and where they reach a board it is through Vivado or Quartus.
Two things exist nowhere on that list: a backward pass running on the chip itself, and a flow with no vendor licence in it. If inference through HLS is what you need, use hls4ml — it is good, it is free, and I would tell you the same in an email.
Video, code, KAT vector sets, community access.
The same, plus remote runs on my Artix-7 boards. No board of your own required.
Live sessions, code review, and your own design gone through with you.
Two days with your engineers around a problem you actually have.
Basic Python and some idea of digital logic is enough. Verilog is taught from scratch, and two of the formats include runs on my hardware.