Blog
Three dies that never reached the foundry become three gateware layers on the most-studied FPGA family: attestation at boot, a BLAKE3 receipt per action, a ternary engine with an empty DSP column. The agent-in-a-box exists; the verifiable device exists; the intersection is empty.
Three chips did not reach the foundry. TRI-1 Phi, Euler and Gamma — an attestation die, an audit die and a 32-PE ternary mesh — were submitted to the TTSKY26b shuttle in May, the submission was withdrawn, and the next shuttle showed zero tiles free. What survives is everything except the silicon: CI-green RTL, reproducible GDS builds, conformance vectors, an Apache-2.0 license and a DOI. This post is about the product turn: shipping those three dies as gateware on the most-studied FPGA family in the world, under a name that states the claim — TRI CLAW, an agent you can audit.
The agent-in-a-box already exists: a Jetson Orin Nano appliance with an agent stack preinstalled sells for 549 euro. It runs on closed silicon and offers no way to verify what it did. The verifiable device already exists too: Precursor raised over 220,000 dollars on Crowd Supply for a pocket computer whose processor is instantiated on a Spartan-7 FPGA precisely so the owner can inspect it — and its author chose the 7-series because it is the most-studied silicon available. And ternary LLM inference on FPGAs is the hottest corner of the academic edge-AI literature — TeLLMe reports 9 tokens per second at 7 watts with 1.58-bit weights, TerEffic reports 16,300 tokens per second on a 370M model held fully on-chip — yet none of it ships as a product, and none of it sells verification.
| Who | What | What is missing |
|---|---|---|
| Jetson agent boxes | agent appliance, closed silicon | no attestation, no receipts, no open bitstream |
| Precursor | verifiable pocket computer on FPGA | no AI |
| TeLLMe / TerEffic / LUT-LLM / Hummingbird+ | ternary LLM engines on FPGA | papers, not products; verification is not the point |
| TRI CLAW | the intersection | exists as a concept and three gateware layers; see the open questions |
The toolchain underneath is the open one: yosys and nextpnr-xilinx, the place-and-route layer that carries twenty-seven of my merged changes. The arithmetic underneath is the proven one: the closure argument behind the ternary path is machine-checked in Coq, twenty-two theorems with no admitted lemmas. The LUT economics underneath are the measured ones: a ternary dot-product node costs 1.4-1.9x fewer LUTs than int4 and 3.2-4.1x fewer than int8 across fan-in 8 to 64, post-synthesis, on an unfolded node, with the non-monotonic per-weight series (56.2, 75.4, 66.8, 68.1) stated rather than smoothed. The academic field converged on table-lookup matmul for exactly this weight family, which reads to me as independent confirmation that ternary belongs in LUTs.
The open flow ends at the Xilinx 7-series, and I have said plainly elsewhere that no open flow reaches UltraScale+ today. For an agent that sells trust, the limit inverts: the 7-series is the family that has been reverse-engineered, documented and studied for a decade — the same reasoning Precursor used when it picked a Spartan-7 for a security device. TRI CLAW targets the silicon you can distrust productively.
Work with me
I audit RTL and build independent, bit-exact models, then take the result through synthesis and, when useful, onto an Artix-7 board. The first conformance module is free.