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Ternary won the wire; it did not win the gate

2026-08-22 · 9 min read

Base economy is a theorem, not a measurement: 5.66 percent in a 1950 vacuum-tube cost model, a win on the wire in USB4 v2 and GDDR7, and a loss at the gate on noise margin.

[Sources — not one measurement of ours] The case for base three arrives as one number: base 3 is more economical than base 2. The number is exactly right, and it says nothing about hardware, because it is a theorem and not a result. The measurement worth making is named at the end.

The optimum is Steiner’s, 1850; the 5.66 percent is arithmetic

In the classical metric the cost of representing N in base b is the digit count times the base: E(b, N) = b · ⌊log_b(N) + 1⌋, and E/ln(N) tends to b/ln(b). Over the reals that minimum sits at e; the problem was posed and solved by Jakob Steiner in 1850 (Journal für die reine und angewandte Mathematik, vol. 40, p. 208). The comparison of 2 against 3 is not his — it is one division.

2.88539 / 2.73072 = 1.0566: ternary is asymptotically more economical than binary by 5.66 percent — not by a factor. Base 2 and base 4 tie exactly, because 4 = 2². One line checks it:

python3 -c "import math; print([(b, round(b/math.log(b), 5)) for b in (2, math.e, 3, 4, 10)])"

The metric describes a ring counter made of vacuum tubes

The model behind E(b, N) is explicit: a digit with b states costs exactly b units of hardware. It is Engineering Research Associates, High-Speed Computing Devices (McGraw-Hill, 1950): a ring counter on triodes, where base R needs R triodes per digit. Their tube count up to 10⁶ is 39.20 for base 2 against 38.24 for base 3 — 2.5 percent, not 5.66. The same pages carry a caveat the citing literature drops:

"the choice of 2 as a radix is frequently justified on more complete analysis" — ERA, High-Speed Computing Devices, 1950, pp. 84–87.

A CMOS transistor has no "b states at price b". Steve Weis recalls that the model already failed in the tube era: the IBM 650 used bi-quinary, seven triodes per decimal digit. Change the cost function and the optimum moves — Georgiou (arXiv:1611.03715) reports values from 1.42 to 3.83 across his parameters.

On small ranges binary is the economical one

Averaged, not asymptotic, values (Wikipedia, Optimal radix choice): binary wins the first two rows outright, and ternary overtakes only at ranges of order hundreds.

Setun: what is known, and what does not agree

Moscow State University computing centre, Brusentsov’s laboratory, initiated by academician Sobolev; first unit 1958–1959. 200 kHz, about 4500 operations per second, a word of 9 or 18 trits, series production 1961–1965 in Kazan. How many were built is unsettled: 50 in the English Wikipedia, computer-museum.ru and Hayes, 46 in the Russian one. Why it stopped is unsettled too — a price unprofitable for the plant, an administrative decision, or no stated cause.

Hayes records the part that matters: each trit was a pair of ferrite cores, and two cores hold more than one trit. On paper 18 trits span 3¹⁸ = 387,420,489 at r·w = 54 against 58 for the binary equivalent — in the iron that margin went into the implementation. Setun-70 (April 1970) stayed a single unit; its instruction set later became DSSP, on binary machines.

Balanced ternary is beautiful arithmetic

• The range of n trits is symmetric, ±(3ⁿ−1)/2: ±193,710,244 for 18 trits, where two’s complement is asymmetric by one.
• The sign is the sign of the most significant non-zero digit; there is no sign bit.
• Negation is a digit-wise swap of 1 and T, with no carries.
• Truncation is round-to-nearest by construction.
• One number takes ln2/ln3 ≈ 63 percent of the binary digit count.

Knuth calls this notation perhaps the prettiest number system of all. But these are properties of a notation, not of devices.

Ternary won the wire

USB4 Version 2.0 (USB-IF, October 2022), Gen4: three levels, 25.6 GBd per lane, 11 bits into 7 trits because 2¹¹ = 2048 ≤ 3⁷ = 2187 — 99.1 percent of the ternary bound, and the error metric is named TER. GDDR7 followed: JESD239, 5 March 2024, the first JEDEC DRAM standard with PAM — 3 bits in 2 clocks where NRZ moves 2.

Two rows close a common claim: 2.5GBASE-T and 5GBASE-T are not PAM-3 but a downclocked 10GBASE-T with PAM-16 and 128-DSQ, confused with the neighbouring 2.5GBASE-T1 (802.3ch, PAM-4). And PAM-3 is signalling on a wire, not computing: both ends of the link are binary.

It did not win the gate

With a swing Vpp and m equally spaced levels the spacing is Vpp/(m−1): two levels to three halves the noise margin, 6.02 dB, for a density gain of log₂3 = 1.58×. The USB-IF table: relative margin 1 for PAM-2, 0.5 for PAM-3, 0.33 for PAM-4. Ethernet shows the same coefficient — five-level 1000BASE-T needs roughly 6 dB more SNR than three-level 100BASE-T.

The second obstacle is the device. A CMOS gate is a switch with two rails and no static current; a middle level has to be manufactured, by a divider that burns current — as in the 2005 CNTFET ternary inverter, a resistive design that lives in HSPICE and not in silicon — or by multi-threshold devices outside mainstream CMOS. Then the field criticised itself: Etiemble (arXiv:2207.04839) puts it in his title, ternary and quaternary CNTFET full adders are less efficient than binary ones for carry-propagate adders; Takbiri and co-authors (CSSP, 2019) show published multi-valued noise margins were better than the transfer curves allow.

The third obstacle is the size of the prize: 5.66 percent asymptotically, against an industry that collected as much every few months from Moore scaling, without rebuilding Boolean algebra, EDA, compilers and IEEE 754.

BitNet is not a base

The only working ternary result in ML is BitNet b1.58 (arXiv:2402.17764, February 2024, Microsoft Research and UCAS): weights in {−1, 0, +1}, activations at 8 bits, and "1.58" is log₂3, the entropy of a trit. The zero is the working part — explicit feature filtering. The 2B4T model (arXiv:2504.12285) has 2 billion parameters.

• This is binary hardware with a three-valued weight set: no positional base-3 arithmetic in it, and what removes the multipliers is the set {−1, 0, +1}.
• 1.58 bits is the bound, not what sits in memory: four ternary values are packed into one int8, so 2 bits per weight, 26 percent over.
• The energy column is the report’s model estimate, not a wattmeter reading.
• Neighbouring terms are not ternary: TLC NAND is 3 bits and 8 levels, PAM-4 is four levels, a tri-state buffer in High-Z is a disabled driver.

What this does not establish

• No instrument was used here. Every number above is read off a source, and the post ends with the experiment that would replace them.
• The circulating "8,487 values where ternary loses to binary" count, and the "40× the transistors per trit" figure, have no primary source and are not used as facts.
• A 2019 Nature Electronics paper with a fabricated ternary CNTFET inverter was not found; the Nature 2019 carbon-nanotube RISC-V processor is binary.
• Whether 46 or 50 Setun machines were built is a disagreement between sources, and no RTL resolves it.
• PAM-3 in mainstream FPGA transceivers is unconfirmed: no mention in the checked AMD Versal and Altera Agilex material.
• Native ternary cannot be tested on an FPGA: LUTs and flip-flops are two-level, so a trit is stored as two bits — as in the 5500FP CPU and the Tiny Tapeout calculator. "Ternary is cheaper on FPGA" would measure the emulation penalty.

The honest position is narrow. Base economy is mathematics: exactly true, equal to 5.66 percent, denominated in the triodes of a 1950 ring counter. A result would be a cost function measured on components that exist — the thing Weis says nobody published. The experiment is small: a balanced-ternary adder of N trits at two bits per trit against a binary adder of ⌈N·log₂3⌉ bits of the same dynamic range, LUT, FF and Fmax after place-and-route, N = 9, 18, 24. That is a different currency from the ERA one, and saying so is half the work. The hypothesis is that ternary loses, forfeiting the hardware carry chain. A negative result is the more valuable one: it turns a 76-year-old argument from philosophical into measured.

That is the kind of measurement the Golden Foundry club at t27.ai/#/foundry runs and publishes — with the denominator, the conditions, and negative results set in the same size as positive ones. If the ternary adder loses, the number goes up anyway.