Blog
[measured] A merged fp6_e3m2 correction changed 8 boundary codes, kept 56 codes unchanged, and brought a 66,720-code consistency pass to 0 mismatches.
[measured] A merged correction in gHashTag/trinity-fpga aligned the fp6_e3m2 boundary rule across the host conformance path. When the exponent field reaches its maximum, the code now saturates to the largest finite value, 14.0, instead of being read as an ordinary exponent.
[measured] The correction changed 8 boundary codes: four positive and four negative. The remaining 56 fp6_e3m2 codes were unchanged. This is a conformance correction, not a claim about speed, energy, model quality, or a new hardware result.
[proven] The same saturation rule now appears in five places: the fp6_e3m2 RTL, the per-format decode oracle, the shared decode oracle, the host golden implementation, and the self-test vector. A correction in only one of them would leave the next comparison inconsistent.
[measured] The host self-test finished with 53/53 checks passing. A full golden-consistency pass compared 66,720 codes and found 0 mismatches. The oracle comparison reported 8/8 changed boundary codes matching and 56/56 unchanged codes preserved; fp6_e2m3 was left untouched.
[measured] The previous change had made the self-test fail on the same 8 codes. That failure was useful: it showed that the shared oracle had moved ahead of the host golden and its hard-coded vector. The fix was to carry the rule through the remaining artefacts rather than weaken the check.
[proven] During diagnosis, a piped command made a failing self-test appear to exit successfully because the shell reported the status of tail rather than Python. A rerun without the pipe returned the intended failure status. Recording that near-miss matters: the gate was correct; the measurement command was not.
The OCP MX specification was not independently read in this run; the result establishes alignment among the existing RTL and conformance artefacts. The checked worktree did not include the RTL submodule, so no end-to-end run on the binary ALINX AX7203 FPGA was repeated here. One corrected format does not establish correctness of the other formats in the 83-format catalogue, a general hardware result, a physical-chip result, speed, energy, or downstream-model accuracy.
Work with me
I audit RTL and build independent, bit-exact models, then take the result through synthesis and, when useful, onto an Artix-7 board. The first conformance module is free.