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A real value must not travel in an integer container
A merged Verilog-emitter fix moved one simulation case from 5 PASSED / 6 FAILED to 11 PASSED while syntax acceptance stayed at 380 files, showing why form and numerical-meaning gates must be separate.
- THE CONTAINERInteger storage loses the fraction.
- THE CALCULATIONEleven simulation checks now pass.
- THE OTHER GATE380 syntax accepts, before and after.
[measured] A merged t27 change found two places where a real-valued result was forced through an integer container in the Verilog emitter. On specs/trinet/etx.t27 under icarus-simulate, the targeted run moved from 5 PASSED / 6 FAILED with exit code 1 to 11 PASSED with exit code 0.
The file was valid; the calculation was not
One site routed every multiplication through __mul_noop, whose [63:0] inputs rounded a real operand before using it. Thus __mul_noop(0.3, 10.0) produced 0, and ewma_step(5.0, 0.3, 10.0) returned 5.0 instead of 6.5. Another site emitted every given binding as reg [63:0], so ewma_step(0.5, 0.5, 1.0) stored 1 instead of 0.75.
icarus-simulate specs/trinet/etx.t27
before: 5 PASSED / 6 FAILED, exit 1
after: 11 PASSED, exit 0[measured] The change reached 46 of 581 generated Verilog files. Yet iverilog -g2012 accepted 380 files before and after. The stable syntax count is the point: a simulator can accept a file while the generated program computes a different value.
Two checks, not one
A syntactically valid generated file is not evidence that its numerical result is valid.
The patch also keeps a useful negative result. Five mutations of this defect were killed by tests, but that is evidence about this test set, not a certificate for the whole compiler. The unchanged iverilog acceptance count does not establish computational equivalence either.
What remains open
- Correctness of all real-valued operations, all specifications, and every backend was not established.
- The result does not measure speed, FPGA area, energy, or downstream model quality.
- Verilog real is simulation-only; this icarus-simulate result is not a synthesis result.
- The five killed mutations show that the selected tests catch these variants, not that unseen variants cannot survive.
For an engineering pipeline, keep the gates separate: one asks whether the simulator accepts the generated file, and another compares its numerical result with an independent expected value. The form gate checks shape; the meaning gate checks the calculation.
What this does not settle
- Correctness of all real-valued operations, all specifications, and every backend was not established.
- The result does not measure speed, FPGA area, energy, or downstream model quality.
- Verilog real is simulation-only; this icarus-simulate result is not a synthesis result.
- The five killed mutations show that the selected tests catch these variants, not that unseen variants cannot survive.
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