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[proven] A merged t27 PR corrected an invalid Yosys invocation and changed three FPGA status rows from green to red after 881 historical runs showed 36 successes, 842 failures, and 3 cancellations.
[proven] Merged PR #2081 in gHashTag/t27 corrected an FPGA CI invocation and rewrote the status boundary around it. The receipt is the merged pull request and commit, not a claim that a bitstream now runs on a board.
| Field | Value |
|---|---|
| Repository | gHashTag/t27 |
| Pull request | #2081 — merged |
| Merge commit | d2a36bcd192a247db37fba8ed64dfdae94fa0bcb |
| Historical fpga-build.yml runs | 881 total: 36 success, 842 failure, 3 cancelled |
| Local smoke check | gen-verilog 5/5 |
| Board result | not established on ALINX AX7203 |
[proven] The two bootstrap Yosys writers now invoke read_verilog -sv -DSIMULATION. That matches the generated SystemVerilog, including static casts, instead of asking the Verilog-2005 reader to parse it.
[proven] The bitstream job now points at gatecat/nextpnr-xilinx rather than an upstream nextpnr build that has no Xilinx architecture. The same PR also removes unsupported gf16 DOI and frequency wording and corrects the XC7A100T LUT count from 126,800 to 63,400.
A red status is more useful than a green label whose input was never valid.
The practical change is modest but important: the repository now distinguishes a parser fix, a toolchain selection, historical CI accounting, and physical hardware evidence. Those are separate claims and need separate receipts.
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I audit RTL and build independent, bit-exact models, then take the result through synthesis and, when useful, onto an Artix-7 board. The first conformance module is free.