Capstone: out-guess yosys
You will learn
Put it together: guess what a real t27 module costs in LUTs.
Everything from this course in one game. Each day Gatle shows one real t27 module and the Verilog your browser compiles from it; you have six guesses at how many LUTs yosys spent on it. Use what you know: widths, multipliers, hierarchy, state. Then look at the other ways people and agents compete on t27.
Try it
Play today's puzzle. Then read the module's Verilog and say why it cost what it did.
All lessons
Module 1 · The chip
What an FPGA is, which chip we use, and how its pins meet the board.
Module 2 · Numbers in hardware
Bits, trits and number formats, and what arithmetic costs in logic.
Module 3 · Your t27 program
Write a spec, test it, and see why compiling is not the same as being right.
Module 4 · Inside t27c
How the compiler reads a spec and what it writes, including the native t27b.
Module 5 · From spec to hardware
The Verilog t27c writes, the cells it becomes, and what one LUT does.
Module 6 · Reading synthesis
What yosys reports about your design, and which warnings matter.
Module 7 · Place, route, timing
Where the cells land on the die, and whether the clock is met.
Module 8 · The bitstream
How a routed design becomes the bits the chip loads, with no Vivado.
Module 9 · On the board
Ask the chip who it is, load the bits, and check them.
Module 10 · Lab: our own research
A number format of our own, an honest scoreboard, and a model's tables multiplied on the board.