Seven backends, and t27b
You will learn
One spec, many target languages, and a native compiler with no LLVM.
One t27 spec can become Zig, C, Rust, JavaScript, TypeScript or Verilog; Verilog comes two ways, straight from the spec and through the HIR, which makes seven backends. The player shows the Rust t27c writes for hello_world. t27b is a second compiler: native AArch64 machine code, no LLVM, a JIT for tests and Mach-O object files. It is not finished, and we say how far it is: in run 26c447ad8 it passed 307 of the 449 specs that the reference compiler passes with tests, 68.4%.
Try it
Switch the player to JavaScript under Also try, generate the module, and run it.
Open the lesson's spec in the player: specs/tutorial/08_modules_and_arrays.t27
All lessons
Module 1 · The chip
What an FPGA is, which chip we use, and how its pins meet the board.
Module 2 · Numbers in hardware
Bits, trits and number formats, and what arithmetic costs in logic.
Module 3 · Your t27 program
Write a spec, test it, and see why compiling is not the same as being right.
Module 4 · Inside t27c
How the compiler reads a spec and what it writes, including the native t27b.
Module 5 · From spec to hardware
The Verilog t27c writes, the cells it becomes, and what one LUT does.
Module 6 · Reading synthesis
What yosys reports about your design, and which warnings matter.
Module 7 · Place, route, timing
Where the cells land on the die, and whether the clock is met.
Module 8 · The bitstream
How a routed design becomes the bits the chip loads, with no Vivado.
Module 9 · On the board
Ask the chip who it is, load the bits, and check them.
Module 10 · Lab: our own research
A number format of our own, an honest scoreboard, and a model's tables multiplied on the board.