From a spec to Verilog
You will learn
How a t27 function becomes logic, and how a clocked function becomes registers.
Verilog is the text a synthesizer reads to build a circuit. t27c writes it from the spec. A function named on_clock becomes an always block on the clock edge, and every module var becomes a register with a reset. Open clocked_counter.t27 in the player: an 8-bit counter in a few lines, and the Verilog it turns into. Its header records what yosys built from it.
Try it
Open clocked_counter.t27 in the player and find the always block in its Verilog tab.
Open the lesson's spec in the player: specs/ternary/clocked_counter.t27
All lessons
Module 1 · The chip
What an FPGA is, which chip we use, and how its pins meet the board.
Module 2 · Numbers in hardware
Bits, trits and number formats, and what arithmetic costs in logic.
Module 3 · Your t27 program
Write a spec, test it, and see why compiling is not the same as being right.
Module 4 · Inside t27c
How the compiler reads a spec and what it writes, including the native t27b.
Module 5 · From spec to hardware
The Verilog t27c writes, the cells it becomes, and what one LUT does.
Module 6 · Reading synthesis
What yosys reports about your design, and which warnings matter.
Module 7 · Place, route, timing
Where the cells land on the die, and whether the clock is met.
Module 8 · The bitstream
How a routed design becomes the bits the chip loads, with no Vivado.
Module 9 · On the board
Ask the chip who it is, load the bits, and check them.
Module 10 · Lab: our own research
A number format of our own, an honest scoreboard, and a model's tables multiplied on the board.