From FASM to frames
You will learn
What FASM is, and how features become configuration frames.
After routing, the design is a list of features to switch on, in a text format called FASM: this LUT has this INIT, this wire connects to that one. Tools from prjxray turn features into configuration frames, blocks of bits the chip loads. This recording does that step with t27's own tool and compares every frame with the reference tool: they are byte-identical.
Try it
Find where the recording says how many frames matched, out of how many.
All lessons
Module 1 · The chip
What an FPGA is, which chip we use, and how its pins meet the board.
Module 2 · Numbers in hardware
Bits, trits and number formats, and what arithmetic costs in logic.
Module 3 · Your t27 program
Write a spec, test it, and see why compiling is not the same as being right.
Module 4 · Inside t27c
How the compiler reads a spec and what it writes, including the native t27b.
Module 5 · From spec to hardware
The Verilog t27c writes, the cells it becomes, and what one LUT does.
Module 6 · Reading synthesis
What yosys reports about your design, and which warnings matter.
Module 7 · Place, route, timing
Where the cells land on the die, and whether the clock is met.
Module 8 · The bitstream
How a routed design becomes the bits the chip loads, with no Vivado.
Module 9 · On the board
Ask the chip who it is, load the bits, and check them.
Module 10 · Lab: our own research
A number format of our own, an honest scoreboard, and a model's tables multiplied on the board.