Count the cells
You will learn
How to count what a synthesizer built: LUTs, flip-flops, DSPs, block RAM.
After synthesis, yosys can print what it built as JSON: how many LUTs, flip-flops, DSPs and block RAMs. Those counts are an honest measure of a design before place and route. Paste a stat -json from yosys into the stat card, or open the real sample, and get a card and a README badge that say plainly that they are a synthesis count.
Try it
Open the real sample, then read the LUT and FF counts on the card.
Open the lesson's spec in the player: specs/tutorial/04_control_flow.t27
All lessons
Module 1 · The chip
What an FPGA is, which chip we use, and how its pins meet the board.
Module 2 · Numbers in hardware
Bits, trits and number formats, and what arithmetic costs in logic.
Module 3 · Your t27 program
Write a spec, test it, and see why compiling is not the same as being right.
Module 4 · Inside t27c
How the compiler reads a spec and what it writes, including the native t27b.
Module 5 · From spec to hardware
The Verilog t27c writes, the cells it becomes, and what one LUT does.
Module 6 · Reading synthesis
What yosys reports about your design, and which warnings matter.
Module 7 · Place, route, timing
Where the cells land on the die, and whether the clock is met.
Module 8 · The bitstream
How a routed design becomes the bits the chip loads, with no Vivado.
Module 9 · On the board
Ask the chip who it is, load the bits, and check them.
Module 10 · Lab: our own research
A number format of our own, an honest scoreboard, and a model's tables multiplied on the board.