Compiles is not the same as correct
You will learn
Why green checks are not proof, and how to catch code that compiles and is wrong.
A compiler that accepts your code only tells you the code is well formed. It does not tell you the code means what you meant. This recording shows a tool that found specs which compile, pass every gate and are still read wrongly. The lesson for hardware is sharper still: a bug in silicon cannot be patched. Plant a bug yourself in the mutation recording and watch the tests catch it.
Try it
Open the mutation recording under Also try and count how many planted bugs the tests caught.
Open the lesson's spec in the player: specs/tutorial/03_operators.t27
All lessons
Module 1 · The chip
What an FPGA is, which chip we use, and how its pins meet the board.
Module 2 · Numbers in hardware
Bits, trits and number formats, and what arithmetic costs in logic.
Module 3 · Your t27 program
Write a spec, test it, and see why compiling is not the same as being right.
Module 4 · Inside t27c
How the compiler reads a spec and what it writes, including the native t27b.
Module 5 · From spec to hardware
The Verilog t27c writes, the cells it becomes, and what one LUT does.
Module 6 · Reading synthesis
What yosys reports about your design, and which warnings matter.
Module 7 · Place, route, timing
Where the cells land on the die, and whether the clock is met.
Module 8 · The bitstream
How a routed design becomes the bits the chip loads, with no Vivado.
Module 9 · On the board
Ask the chip who it is, load the bits, and check them.
Module 10 · Lab: our own research
A number format of our own, an honest scoreboard, and a model's tables multiplied on the board.