The stages of t27c
You will learn
The path a spec takes inside t27c: tokens, syntax tree, types, HIR, code.
t27c reads a spec in stages. The lexer cuts the text into tokens. The parser builds a syntax tree. The type checker checks every width and every call. The tree is lowered to HIR, a simpler form, and each backend writes code from it. This widget runs those stages on a spec in your browser and shows what each one produced, so an error has a stage you can point at.
Try it
Pick an example and step through the stages; find the stage where a type error would stop.
Open the lesson's spec in the player: specs/tutorial/06_structs_enums_switch.t27
All lessons
Module 1 · The chip
What an FPGA is, which chip we use, and how its pins meet the board.
Module 2 · Numbers in hardware
Bits, trits and number formats, and what arithmetic costs in logic.
Module 3 · Your t27 program
Write a spec, test it, and see why compiling is not the same as being right.
Module 4 · Inside t27c
How the compiler reads a spec and what it writes, including the native t27b.
Module 5 · From spec to hardware
The Verilog t27c writes, the cells it becomes, and what one LUT does.
Module 6 · Reading synthesis
What yosys reports about your design, and which warnings matter.
Module 7 · Place, route, timing
Where the cells land on the die, and whether the clock is met.
Module 8 · The bitstream
How a routed design becomes the bits the chip loads, with no Vivado.
Module 9 · On the board
Ask the chip who it is, load the bits, and check them.
Module 10 · Lab: our own research
A number format of our own, an honest scoreboard, and a model's tables multiplied on the board.