Who holds the IO
You will learn
Who holds the bench IO right now, and what the registered clients declare.
Real hardware shared is hardware borrowed: the bench registers its IO clients, and the recording reads them live -- names, claims and what each declares it owns. The spec is the tool card of tri fpga-ioclients. The lesson closes the loop the course opened: a bus, its spec, its bench, and now the hands on it.
Try it
In the recording, list the clients the bench reports; then in the spec frame find what a client must declare to register.
The registered IO clients on the bench, read live: names, claims and what each client declares it owns.
specs/tools/trios/tri/fpga-ioclients.t27
// SPDX-License-Identifier: Apache-2.0
; specs/tools/trios/tri/fpga-ioclients.t27 -- tool gHashTag/BrowserOS:tri/fpga-ioclients, the `tri fpga-ioclients` command of the trios loop CLI
; Generated by apps/website/scripts/tools-from-trios-tri.mjs from gHashTag/BrowserOS:trios/bin/tri at 7366096248df; do not edit.
; The CLI the loop timers run (`tri drift` holds ~/.local/bin/tri to the tracked copy). It is another program than
; the Rust tri of gHashTag/t27 and the Zig tri of gHashTag/trinity, so the ID is repository-qualified.
; A card is data and carries no test block. ASCII only (L3). phi^2 + 1/phi^2 = 3 | TRINITY
module tool_trios_tri_fpga_ioclients;
pub const KIND : str = "tool";
pub const FAMILY : str = "tri-cli";
pub const ID : str = "gHashTag/BrowserOS:tri/fpga-ioclients";
pub const REPO : str = "gHashTag/BrowserOS";
pub const QUALIFIED_ID : str = "gHashTag/BrowserOS:tri/fpga-ioclients";
pub const SCHEMA : u32 = 2;
pub const COMMAND : str = "tri fpga-ioclients";
; The case arm of the dispatcher and the first line of it that does the work.
pub const VARIANT : str = "case arm `fpga-ioclients)`, line 1951";
pub const SOURCE : str = "trios/bin/tri";
pub const ENTRY : str = "trios/bin/tri";
pub const SOURCE_COMMIT : str = "7366096248dfb09893e9a7d1a0f1c56ced13d16e";
pub const ROUTED : bool = true;
pub const DISPATCH : str = "exec python3 \"$HOME/skills/ax7203-board-loop/scripts/board.py\" ioclients";
pub const DOCUMENTED : bool = true;
pub const HELP_LINE : str = "tri fpga-ioclients -- who holds IOKit user clients on the CP2102N (pid, count, alive) and which driver is bound (AppleUSBSLCOM or a vendor one); every fpga-run header gets \"# usb clients\" and \"# usb driver\" lines";
pub const CATEGORY : str = "AX7203 board (tern_tc: receipts, UART, formats)";
pub const ABOUT : str = "who holds IOKit user clients on the CP2102N (pid, count, alive) and which driver is bound (AppleUSBSLCOM or a vendor one); every fpga-run header gets \"# usb clients\" and \"# usb driver\" lines";
pub const ABOUT_SOURCE : str = "`tri help` (the heredoc under the help arm of trios/bin/tri)";
pub const ACTIONS : [0]str = [];
pub const ACTIONS_ABOUT : [0]str = [];
pub const ARGS : [0]str = [];
pub const AGENTS : [0]str = [];
pub const AGENTS_NOTE : str = "No source binds an agent letter to this command: the trios CLI is not named by docs/agents/AGENTS_ALPHABET.md or .claude/agents/*.md of gHashTag/t27.";
pub const WHEN_TO_USE : str = "who holds IOKit user clients on the CP2102N (pid, count, alive) and which driver is bound (AppleUSBSLCOM or a vendor one); every fpga-run header gets \"# usb clients\" and \"# usb driver\" lines";
; public/term/tri-fpga-ioclients/meta.json lists 1 run(s) of `tri fpga-ioclients`, exit 0. The site plays it at the end of this card.
pub const CAST : str = "term/tri-fpga-ioclients/session.cast";
pub const WITNESS : str = "source-parse";
pub const WITNESS_SOURCE : str = "gHashTag/BrowserOS:trios/bin/tri at 7366096248dfb09893e9a7d1a0f1c56ced13d16e, read as text (the help heredoc and the top-level case arms); the CLI was not run";
pub const ENABLED : bool = true;
All lessons
Module 1 · What a bus is
Why a bus exists at all: a conversation on wires, framed and addressed, and who is allowed to talk.
Module 2 · UART
The two-wire bus with no clock: the frame, the divisor that sets the rate, and the status a driver polls.
Module 3 · SPI
The clocked conversation: four modes, a prescaler ladder, and a chip select per servant.
Module 4 · APB
The register bus: PSEL and PENABLE, strobes and wait states, and how many address bits a peripheral count costs.
Module 5 · AXI4
The five channels: address, data and response in both directions, lite or full, bursts and IDs.
Module 6 · Memory
What sits on the far side of every bus: memory maps, port kinds, and latency that a wait state must cover.
Module 7 · Bridges
Why designs grow more than one bus, and the packet bridge that moves work between them.
Module 8 · Ethernet
Frames, the frame check sequence, RGMII timing, and the pre-registered steps of a real bring-up.
Module 9 · The bench
The discipline that guards real hardware: who holds the IO, taking and giving the lock, and what runs next.