Course
Buses and peripherals with t27: UART, SPI, APB, AXI4, Ethernet
It picks up where the clocks course ends. Every lesson opens a real tool or a recording of t27c on a real machine, next to a spec you can run in your browser.
Course 7, 27 lessons, one widget and one t27 spec each: why a bus exists, the UART frame, SPI modes, the APB handshake, the five AXI4 channels, memory maps, bridges, Ethernet frames and RGMII timing, and the bench IO discipline. Every number comes from a spec or a recorded run.
All lessons
Module 1 · What a bus is
Why a bus exists at all: a conversation on wires, framed and addressed, and who is allowed to talk.
Module 2 · UART
The two-wire bus with no clock: the frame, the divisor that sets the rate, and the status a driver polls.
Module 3 · SPI
The clocked conversation: four modes, a prescaler ladder, and a chip select per servant.
Module 4 · APB
The register bus: PSEL and PENABLE, strobes and wait states, and how many address bits a peripheral count costs.
Module 5 · AXI4
The five channels: address, data and response in both directions, lite or full, bursts and IDs.
Module 6 · Memory
What sits on the far side of every bus: memory maps, port kinds, and latency that a wait state must cover.
Module 7 · Bridges
Why designs grow more than one bus, and the packet bridge that moves work between them.
Module 8 · Ethernet
Frames, the frame check sequence, RGMII timing, and the pre-registered steps of a real bring-up.
Module 9 · The bench
The discipline that guards real hardware: who holds the IO, taking and giving the lock, and what runs next.