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Three widgets for the physics under the bus: reflections, a closing eye, an ECC word
[each widget's logic is a t27 spec compiled to wasm; lossless line, one-pole channel, values typed, nothing read from a board] A 1 V step from a 25 ohm driver into an open 50 ohm line reaches the far end as 1.333, 0.889, 1.037, 0.988 V before it settles at 1 V; one RC pole leaves a quarter of the eye at T = TAU and shuts it at TAU ln 2; a 13-bit SECDED word fixes any single flip and catches any two. Three new widgets show this, each running the fn bodies of its own t27 spec, with 20 spec tests and 15 negative controls behind them.
The buses course teaches the protocols: UART, SPI, APB, AXI4, Ethernet. Underneath every one of them is physics the protocol never mentions: a wire is a transmission line, a fast edge does not arrive once, a short bit does not finish rising, and a memory cell can flip. Three new widgets show those three things, and each one computes nothing of its own: its logic is a t27 spec's fn bodies compiled to WebAssembly, so the page draws exactly what the spec's tests assert.
A step down a line arrives more than once
line-bounce runs specs/fpga/line_bounce.t27: a driver of resistance RS sends a step into a line of impedance Z0; each end reflects by (R - Z0) / (R + Z0). With the textbook values of Johnson and Graham -- a 1 V step, RS 25 ohm, Z0 50 ohm, an open end -- the far end reads 1.333 V on the first arrival, then 0.889, 1.037, 0.988, and settles at 1 V. The two reflection coefficients have opposite signs, so it rings. A series resistor that makes RS equal Z0 lands it on 1 V at the first arrival; a 50 ohm load at the far end stops the reflection altogether.
A short bit does not finish rising
eye-isi runs specs/fpga/eye_isi.t27: one RC pole of time constant TAU, sampled at the end of each bit, gives y[n] = a y[n-1] + (1 - a) x[n] with a = exp(-T/TAU). The worst 1 reaches 1 - a and the worst 0 stays at a, so the eye is 1 - 2a: a quarter of the swing at T = TAU, and shut at T = TAU ln 2. The widget pushes two periods of PRBS7 through the channel and measures the eye it drew: 26.5% at T = TAU, against the formula's worst case of 26.4% (PRBS7 has no infinitely long run). At T = 0.6 TAU the eye is shut; a 25% de-emphasis tap opens it to 21.6%. exp itself is in the spec, as a series, with tests.
One flip is fixed, two are caught
ecc-secded runs specs/fpga/secded.t27: 8 data bits, Hamming check bits at positions 1, 2, 4 and 8, and an overall parity bit at 0 -- the construction ECC memory uses per word at 72 bits. Press any bit to flip it: the syndrome is that bit's position in binary, and the byte comes back. Flip two and the parity stays even while the syndrome is not zero: detected, not corrected. The spec's tests check every byte, every single flip and every pair of flips of three words.
What these do not show
- The line is lossless, the load is a resistor and the edge is ideal; a real trace has loss, vias and a pin capacitance.
- One pole is the mechanism of intersymbol interference, not a link budget: no jitter, crosstalk or receiver noise.
- Three or more flips can alias to one in SECDED and be corrected wrongly; the widget says so.
Try them
- t27.ai/widgets/line-bounce/
- t27.ai/widgets/eye-isi/
- t27.ai/widgets/ecc-secded/
- The specs: gHashTag/t27 specs/fpga/line_bounce.t27, eye_isi.t27, secded.t27
What this does not settle
- The line is lossless and the load a resistor; no trace on our board was measured for this post.
- One pole is the mechanism of ISI, not a link budget: no jitter, crosstalk or receiver noise.
- Three or more flips can alias to one in SECDED; the widget states it, the tests do not cover it.
Receipts
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