Verification service
Send your RTL. It runs on a real Xilinx Artix-7 and comes back with a signed report: bit-exact conformance against an independent model, achieved timing, resource usage, and the bitstream — on a fully open-source toolchain, so every number can be reproduced.
Every node of your datapath checked against an independent reference model with known-answer vectors. Divergence between specification and RTL surfaces before synthesis, not after tape-out.
Achieved frequency, slack, LUT/FF/BRAM/DSP usage and a latch-free check — measured on a live Artix-7, not estimated from a report.
Bitstream, test vectors, logs and the exact toolchain versions, so anyone can re-run the whole flow themselves.
Yosys, nextpnr-xilinx, prjxray, openFPGALoader, iverilog. Nothing in the report depends on a proprietary licence you would need to buy.
And say what “correct” means for it.
Written from the operation, never from your RTL — a testbench derived from the same assumptions as a design agrees with the design's bugs.
Measured numbers, vectors, bitstream, and every command needed to reproduce it.
One module or IP core: bit-exact check, timing, resources, report.
A full block with multiple cores, integration checks and a written analysis.
Everything above plus the preparation a shuttle submission needs.
Ongoing verification as your design changes.
Measurements come from a Xilinx Artix-7. This is not multi-corner characterisation and does not claim to be.
It is an independent check, not a substitute for a full commercial sign-off.
I verify what I can read. Encrypted IP cannot be checked this way.
Anything estimated rather than measured says so, here and in every report.
Have a design to verify? The first module is free, so you can judge the report before paying for anything.