From zero to a chip: FPGA programming with t27

All lessons

• Module 1 · The chip

  What an FPGA is, which chip we use, and how its pins meet the board.

  1. 01 An FPGA is a grid you configure
  2. 02 Which chip is this?
  3. 03 Pins, balls and the package

• Module 2 · Numbers in hardware

  Bits, trits and number formats, and what arithmetic costs in logic.

  1. 04 Bits, trits and GF16
  2. 05 What arithmetic costs
  3. 06 How much fits on the chip

• Module 3 · Your t27 program

  Write a spec, test it, and see why compiling is not the same as being right.

  1. 07 Hello, t27
  2. 08 Tests are part of the spec
  3. 09 Compiles is not the same as correct

• Module 4 · Inside t27c

  How the compiler reads a spec and what it writes, including the native t27b.

  1. 10 The stages of t27c
  2. 11 t27c on a real machine
  3. 12 Seven backends, and t27b

• Module 5 · From spec to hardware

  The Verilog t27c writes, the cells it becomes, and what one LUT does.

  1. 13 From a spec to Verilog
  2. 14 Count the cells
  3. 15 One LUT, up close

• Module 6 · Reading synthesis

  What yosys reports about your design, and which warnings matter.

  1. 16 Synthesis warnings that matter
  2. 17 State machines
  3. 18 Where the LUTs go

• Module 7 · Place, route, timing

  Where the cells land on the die, and whether the clock is met.

  1. 19 Placement: where the cells land
  2. 20 Logic depth
  3. 21 Timing and slack

• Module 8 · The bitstream

  How a routed design becomes the bits the chip loads, with no Vivado.

  1. 22 From FASM to frames
  2. 23 A build, itemised
  3. 24 Read a bitstream

• Module 9 · On the board

  Ask the chip who it is, load the bits, and check them.

  1. 25 JTAG asks the chip
  2. 26 The same bits, on the board
  3. 27 Capstone: out-guess yosys

• Module 10 · Lab: our own research

  A number format of our own, an honest scoreboard, and a model's tables multiplied on the board.

  1. 28 T27: a number format of our own
  2. 29 An honest scoreboard
  3. 30 A model's tables on the board