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A small complete program

You will learn

How the pieces of this course make one spec that becomes a circuit.

The lesson spec has a module line, a width constant, test values and on_comb, a function of two u8 inputs. gen-verilog turns it into a module whose ports are a clock, a reset and an enable, the two 8-bit inputs a and b, a ready output and the 8-bit output result. An assign line sets result from on_comb, so the sum itself waits for no clock edge. The tests check the example sums as constants; the site runner does not call on_comb, so the check of the circuit itself is left to a simulator.

Try it

Open the verilog tab of the lesson spec in the player and find the input, output and assign lines.

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t27 basics 26: an adder in t27 and its Verilog ports
t27 basics 26: an adder in t27 and its Verilog ports ↗

An 8-bit adder written in t27, with the Verilog ports and assign line the real compiler wrote for it. Lesson 26 of the t27 basics course.

specs/basics/26_a_small_program.t27

// SPDX-License-Identifier: Apache-2.0
; t27 basics, lesson 26: A small complete program.
; An 8-bit adder in t27, its tests, and the Verilog ports t27c writes for it.

module basics_26_a_small_program;

pub const WIDTH : u8 = 8;
pub const A_EXAMPLE : u8 = 100;
pub const B_EXAMPLE : u8 = 55;
pub const SUM_EXAMPLE : u8 = 155;

fn on_comb(a: u8, b: u8) -> u8 {
    return a + b;
}

test the_example_sum_fits_in_a_byte {
    assert A_EXAMPLE + B_EXAMPLE == SUM_EXAMPLE;
    assert SUM_EXAMPLE <= 255;
}

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