Every design put through the open flow, newest set first. Mine are listed alongside other people's on purpose: two of mine failed a check that all three of theirs passed, and hiding that would make the rest worth less.
| Design | Whose | Top module | Checks | Run |
|---|---|---|---|---|
| Quantum Brain HOLOGRAPHIC | mine | tt_um_qbrain_holo | 5/5 | 2026-08-11 |
| Quantum Brain MINI | mine | tt_um_qbrain_mini | 5/5 | 2026-08-11 |
| TRI-1 Euler | mine | tt_um_ghtag_trinity_gf16 | 5/5 | 2026-08-11 |
| TRI-1 Gamma | mine | tt_um_trinity_max_true | 5/5 | 2026-08-11 |
| TRI-1 Phi | mine | tt_um_trinity_nano | 5/5 | 2026-08-11 |
| Float synth | third party | tt_um_float_synth_nikleberg | 5/5 | 2026-08-11 |
| SERDES | third party | tt_um_serdes | 5/5 | 2026-08-11 |
| SERV RISC-V SoC on Wishbone | third party | tt_um_divadnauj_GB_serv_soc_wb | 5/5 | 2026-08-11 |
| Stochastic neuron | third party | tt_um_santhosh_stoch_neuron | 5/5 | 2026-08-11 |
| TinyGPU v2 | third party | tt_um_pongsagon_tinygpu_v2 | 5/5 | 2026-08-11 |
Toolchain for every row above: Yosys 0.65 (git sha1 aec814bdf3071f7e0fd0fbe43f7f711e99d01e24) · Icarus Verilog 13.0 (stable, v13_0)