SERV RISC-V SoC on Wishbone

A bit-serial RISC-V core with a Wishbone SoC around it, across 40 declared files.

divadnauj-GB/tt_um_divadnauj-GB_serv_soc_wb · top tt_um_divadnauj_GB_serv_soc_wb · 5 of 5 checks passed

divadnauj-GB/tt_um_divadnauj-GB_serv_soc_wb · 2026-08-11 · Yosys 0.65 (git sha1 aec814bdf3071f7e0fd0fbe43f7f711e99d01e24) · Icarus Verilog 13.0 (stable, v13_0)

PASS sources resolve

40 of 40 declared files found

info.yaml source_files -> src/

PASS elaborates

clean from the declared list alone

iverilog -g2012 -t null -I src -s <top> <declared sources>

PASS no inferred latches

no $_DLATCH_ cells after techmap

yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*

PASS synthesises

8,301 cells including submodules, 4,903 wires. 2,081x $_AND_, 1,957x $_OR_, 1,605x $_MUX_, 689x $_DFFE_PP0P_

yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat

PASS has clocked logic

1,751 flip-flops

yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist

Badge

Shields renders it from a static JSON file served here, so it stays current without anything running.

[![t27.ai](https://img.shields.io/endpoint?url=https://t27.ai/r/divadnauj-GB/tt_um_divadnauj-GB_serv_soc_wb/badge.json)](https://t27.ai/r/divadnauj-GB/tt_um_divadnauj-GB_serv_soc_wb/)

What this does not establish

A pass is not a proof of correctness. These checks say the design elaborates, infers no latches, synthesises and contains clocked logic. None of them compares it against a specification.
Generic yosys cells are not silicon area. Only the real ASIC flow settles whether a design fits its tiles.
No frequency is claimed. Counting flip-flops says a frequency is a meaningful question, not what the answer is.
Nothing here ran on hardware. These are simulation and synthesis results.