TRI-1 Euler

GF16 e-engine, 8x2 tiles.

gHashTag/t27 · chips/euler · top tt_um_ghtag_trinity_gf16 · 5 of 5 checks passed

gHashTag/t27 @ 592ba4c2d · 2026-08-11 · Yosys 0.65 (git sha1 aec814bdf3071f7e0fd0fbe43f7f711e99d01e24) · Icarus Verilog 13.0 (stable, v13_0)

PASS sources resolve

34 of 34 declared files found in src/

info.yaml source_files -> src/

PASS elaborates

clean from the declared list alone

iverilog -g2012 -t null -I src -s tt_um_ghtag_trinity_gf16 src/*.v

PASS no inferred latches

no $_DLATCH_ cells after techmap

yosys: select -assert-none t:$_DLATCH_* t:$_DLATCHSR_*

PASS synthesises

39,991 cells including submodules, 37,170 wires. 18,083x $_MUX_, 8,073x $_AND_, 5,823x $_OR_, 5,469x $_XOR_

yosys: read; hierarchy -top; proc; opt; fsm; memory; techmap; flatten; stat

PASS has clocked logic

473 flip-flops

yosys stat: sum of $_DFF*/$_SDFF*/$_ADFF* cells in the flattened netlist

Badge

Shields renders it from a static JSON file served here, so it stays current without anything running.

[![t27.ai](https://img.shields.io/endpoint?url=https://t27.ai/r/gHashTag/t27/chips/euler/badge.json)](https://t27.ai/r/gHashTag/t27/chips/euler/)

What this does not establish

A pass is not a proof of correctness. These checks say the design elaborates, infers no latches, synthesises and contains clocked logic. None of them compares it against a specification.
Generic yosys cells are not silicon area. Only the real ASIC flow settles whether a design fits its tiles.
No frequency is claimed. Counting flip-flops says a frequency is a meaningful question, not what the answer is.
Nothing here ran on hardware. These are simulation and synthesis results.