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Plan before code

You will learn

How a verification plan is a checklist that a command can sweep and sign.

A test plan written after the code is a description of what the code does; written before, it is a claim the code must live up to. In this repo the plan is a spec, and a command sweeps it. The widget is that sweep for the bench tools: 14 of 14 pass their own self-tests in one run -- decode 18/18, repin 17/17 -- and any tool that cannot check itself is listed, not waved through. The lesson's spec is build_verify: the checklist of what a build must show before anyone calls it done.

Try it

Run the tool sweep and find the one tool whose self-test is listed rather than run; then read build_verify's checklist and mark which items are counts and which are claims.

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tri fpga-tools · 14 bench tools test themselves
tri fpga-tools · 14 bench tools test themselves ↗

14 of 14 bench tools pass their own self-tests in one sweep: decode 18/18, repin 17/17, firelog 10/10, tmpcheck 9/9, stamps 9/9, keep 9/9, jtag and seeds PASS.

specs/fpga/verification/build_verify.t27

// SPDX-License-Identifier: Apache-2.0
// t27/specs/fpga/verification/build_verify.t27
// FPGA Build Verification Spec
// Validates all FPGA specs can generate Verilog and pass structural checks
// phi^2 + 1/phi^2 = 3 | TRINITY

module BuildVerify {
    const TOTAL_FPGA_MODULES : u32 = 33;
    const TOTAL_TESTBENCHES : u32 = 30;
    const TOTAL_BOARD_CONFIGS : u32 = 3;
    const TOTAL_SPECS : u32 = 66;
    const NUM_BACKENDS : u32 = 4;
    const VERILOG_FILES : u32 = 66;

    struct ModuleReport {
        name : str;
        verilog_lines : u32;
        has_tests : bool;
        has_invariants : bool;
        has_bench : bool;
    }

    struct BuildResult {
        total_specs : u32;
        parse_ok : u32;
        typecheck_ok : u32;
        gen_zig_ok : u32;
        gen_verilog_ok : u32;
        gen_c_ok : u32;
        gen_rust_ok : u32;
        seal_ok : u32;
        failures : u32;
    }

    fn check_build_clean(result : BuildResult) -> bool {
        return result.failures == 0;
    }

    fn coverage_percent(ok : u32, total : u32) -> u32 {
        if total == 0 { return 0; }
        return (ok * 100) / total;
    }

    test test_module_count {
        invariant TOTAL_FPGA_MODULES == 31;
    }

    test test_testbench_count {
        invariant TOTAL_TESTBENCHES == 30;
    }

    test test_board_count {
        invariant TOTAL_BOARD_CONFIGS == 3;
    }

    test test_total_specs {
        invariant TOTAL_SPECS == TOTAL_FPGA_MODULES + TOTAL_TESTBENCHES + TOTAL_BOARD_CONFIGS;
    }

    test test_backend_count {
        invariant NUM_BACKENDS == 4;
    }

    test test_verilog_file_count {
        invariant VERILOG_FILES == TOTAL_SPECS;
    }

    test test_coverage_100 {
        var cov : u32 = coverage_percent(66, 66);
        invariant cov == 100;
    }

    test test_coverage_0 {
        var cov : u32 = coverage_percent(0, 66);
        invariant cov == 0;
    }

    test test_coverage_50 {
        var cov : u32 = coverage_percent(23, 46);
        invariant cov == 50;
    }

    test test_check_build_clean_success {
        var result : BuildResult = BuildResult {
            total_specs: 66,
            parse_ok: 66,
            typecheck_ok: 66,
            gen_zig_ok: 66,
            gen_verilog_ok: 66,
            gen_c_ok: 66,
            gen_rust_ok: 66,
            seal_ok: 66,
            failures: 0
        };
        invariant check_build_clean(result) == true;
    }

    test test_check_build_clean_failure {
        var result : BuildResult = BuildResult {
            total_specs: 66,
            parse_ok: 65,
            typecheck_ok: 66,
            gen_zig_ok: 66,
            gen_verilog_ok: 66,
            gen_c_ok: 66,
            gen_rust_ok: 66,
            seal_ok: 66,
            failures: 1
        };
        invariant check_build_clean(result) == false;
    }

    invariant total_specs_positive : TOTAL_SPECS > 0;
    invariant no_backend_gaps : NUM_BACKENDS == 4;
    invariant all_backends_equal : VERILOG_FILES == TOTAL_SPECS;
}

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