VCD wrapped: your simulation, summed up on one card

Drop a .vcd from any simulator and get a Wrapped-style card: value changes, the busiest net, signals stuck at X or Z, the quietest ones and the time span, read in your browser.

A file you open here is read by your browser only: it is never uploaded. The page sets no cookie and sends nothing anywhere.

Where the numbers come from

Icarus Verilog version 12.0 (stable), iverilog and vvp; one run per sample, one at a time: iverilog -g2012 -s <top> -o sim.vvp <testbench> <design>; vvp -n sim.vvp; each command, the tool versions and the testbench's verdict lines in samples.json
specs/ternary/clocked_counter.t27, compiled to Verilog by public/t27/t27_compiler.wasm in node (sha256 of spec and generated Verilog in samples.json)
scripts/widget-data/vcd-wrapped-counter-tb.v: a hand-written testbench for the generated ClockedCounter, not from the spec; it checks the spec's own test, hold on en low, the u8 wrap and the asynchronous reset
fpga/openxc7-synth/vsa_bind_16.v with fpga/openxc7-synth/tb/tb_vsa_bind_16.v, and fpga/openxc7-synth/tmu.v with fpga/openxc7-synth/tmu_tb.v, committed RTL and testbenches run unchanged
The VCDs are shipped as vvp dumped them, not trimmed; each is under 200000 bytes
public/widgets/vcd-wrapped/vcdstats.js: the one VCD reader, run in node for the samples and in the browser for your file
node scripts/widget-data/vcd-wrapped.mjs --check: re-reads the shipped VCDs and fails if any K_ fact in this spec disagrees

This widget's .t27 source · All widgets