Synth smells: a lint card for your yosys log

Paste or drop a yosys synth_xilinx log: latches, undriven wires, driver conflicts, memories turned into flip-flops, warnings and final cell counts, read in your browser.

A file you open here is read by your browser only: it is never uploaded. The page sets no cookie and sends nothing anywhere.

Where the numbers come from

Yosys 0.67+post (git sha1 b8e7da6f), one run per sample: yosys -q -l <stem>.full.log -p "read_verilog -sv <stem>.v; synth_xilinx -family xc7 -flatten -top <top>"; every command, exit code and time in samples.json
specs/ternary/stream_ternary_mac.t27, specs/ternary/comb_ternary_dot.t27 and specs/base/ternary_add.t27, compiled to Verilog by public/t27/t27_compiler.wasm in node (sha256 of spec, compiler and Verilog in samples.json)
scripts/widget-data/synth-smells-teaching.v: a hand-written teaching sample, not from a spec, with a latch, an undriven wire, two drivers on one wire and a reset-cleared register file
node scripts/widget-data/synth-smells.mjs: compiles, runs yosys, trims each log by rule (never by hand) and fails unless the full and trimmed log parse to the same counts
public/widgets/synth-smells/smellparse.js: the one parser, run in node for the samples and in the browser for your log
node scripts/widget-data/synth-smells.mjs --check: re-parses the shipped logs and fails if any K_ fact in this spec disagrees

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