LUT explain: a 7-series LUT6 INIT and its FASM line, read as logic

Paste a 64-bit LUT6 INIT or FASM lines: truth table, minimal expression, the gate's name, what each feature sets. Then guess the gate on 4738 LUTs from a routed design.

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Where the numbers come from

node.fasm (sha256 e413fb51f92e88cb...), TRI-NET node v2 for the AX7203 board: part xc7a200tfbg484-2, top trinet_node_v2_ax7203, built in /tmp/x7board/node0 and recorded in its manifest.json
Yosys 0.67+post (git b8e7da6f): synth_xilinx -flatten -abc9 -nocarry -nodsp -arch xc7. nextpnr-xilinx 0.9.2-107-g7037c948: --freq 50 --seed 1 --placer heap --router router1 --timing-allow-fail
prjxray-db ab1fc60, artix7: segbits, ppips and tile_type JSON of CLBLL_L, CLBLL_R, CLBLM_L and CLBLM_R, extracted to prjxray.json
prjxray c9f02d85, CLB fuzzer READMEs 011 to 019 (ffconfig, n5ffmux, ncy0, nffmux, noutmux, precyinit, ram, ndi1mux): what each CLB feature sets
Xilinx UG474, 7 Series FPGAs CLB User Guide: a LUT6 is two LUT5s on shared inputs with outputs O5 and O6
scripts/widget-data/lut-explain.mjs: runs this page's decoder (lut.js) over node.fasm, writes design.json and prjxray.json, and --selftest checks this spec's K_ numbers against them

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