Does it fit, and does it close timing?

Set a filter, its rates and a channel count: watch the 740 DSP slices of an XC7A200T fill, and a register-to-register path race the clock period.

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Where the numbers come from

gHashTag/t27 specs/fpga/dsp/signals.t27 (t27#8985): every value on the page is its fn bodies, compiled to wasm (logic.js)
Xilinx DS180, 7 Series FPGAs Data Sheet: Overview: 740 DSP48E1 slices on the XC7A200T
Xilinx UG479, 7 Series DSP48E1 Slice User Guide: the PCIN/PCOUT cascade that a systolic FIR chains through