Folding a FIR onto DSP slices

Set taps, symmetry, clock and sample rate. Symmetric taps share a multiplier; a fast clock lets one slice serve many taps. See how many slices are left.

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Where the numbers come from

gHashTag/t27 specs/fpga/dsp/signals.t27 (t27#8985): every value on the page is its fn bodies, compiled to wasm (logic.js)
Xilinx UG479, 7 Series DSP48E1 Slice User Guide: the pre-adder that lets symmetric taps share one multiplier
Xilinx DS180, 7 Series FPGAs Data Sheet: Overview: 740 DSP48E1 slices on the XC7A200T

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