The carry chain: why adding is slow, and how a slice makes it fast

Tap the bits of two numbers and watch the carry run up the word. Then set three delays and see what the dedicated carry chain saves over LUTs.

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Where the numbers come from

gHashTag/t27 specs/fpga/dsp/adders.t27 (t27#8985): every value on the page is its fn bodies, compiled to wasm (logic.js)
Xilinx UG474, 7 Series FPGAs CLB User Guide: carry logic, one CARRY4 of 4 bits per slice
Harris and Harris, Digital Design and Computer Architecture, ch. 5: ripple-carry adders