// SPDX-License-Identifier: Apache-2.0
; specs/widgets/basics-a-small-program.t27 -- the infographic of lesson 26 of the t27 basics course (specs/course/t27-basics.t27)
; Source of truth for public/widgets/basics-a-small-program/ (gHashTag/trinity): scripts/widget-pages-from-spec.mjs compiles
; this file, checks its constants, evaluates the tests below and writes the page. tool.js is one import of
; ../infographic.js, which draws SAY_TABLE_* as a real <table> and SAY_FLOW_* as an SVG diagram with a
; <title>, black and white, and holds no words of its own. ASCII only (L3), English only (LANG-EN).
; The lesson spec it illustrates: public/t27/files/specs/basics/26_a_small_program.t27.
; phi^2 + 1/phi^2 = 3 | TRINITY

module widget_basics_a_small_program;

pub const KIND : str = "widget-tool";
pub const ID : str = "basics-a-small-program";
pub const TITLE : str = "t27 basics 26: an adder in t27 and its Verilog ports";
pub const DESCRIPTION : str = "An 8-bit adder written in t27, with the Verilog ports and assign line the real compiler wrote for it. Lesson 26 of the t27 basics course.";
pub const IMAGE_ALT : str = "A black and white diagram of an 8-bit adder from the lesson spec: two 8-bit inputs a and b go into a block and one 8-bit output result comes out; a table lists the ports gen-verilog wrote, clock, reset, enable, a, b, ready and result, and the assign line for result.";
pub const HOOK : str = "Five lines of t27 become an 8-bit adder in Verilog. The ports the compiler wrote.";
pub const CATEGORY : str = "compiler";
pub const DATA_SOURCES : [2]str = ["The lesson spec public/t27/files/specs/basics/26_a_small_program.t27, compiled clean on 7 backends by public/t27/t27_compiler.wasm, whose tests pass in the site test runner", "Compiler verdicts, error lines, code and counts quoted on this page are what the same wasm answered in node 22 when the course was authored; words without a run behind them are said to be read, not run"];
pub const READS_LOCAL_FILES : bool = false;
pub const SENDS_NOTHING : bool = true;

; --- The table -----------------------------------------------------------------------------
pub const SAY_TABLE_CAPTION : str = "gen-verilog on the lesson spec";
pub const SAY_TABLE_HEAD : [1]str = ["Verilog line"];
pub const SAY_TABLE_CELLS : [8]str = ["input wire clk", "input wire rst_n", "input wire en", "input wire [7:0] a", "input wire [7:0] b", "output wire ready", "output wire [7:0] result", "assign result = on_comb(a, b);"];
pub const K_TABLE_COLS : u8 = 1;
pub const K_TABLE_ROWS : u8 = 8;
pub const K_TABLE_CELLS : u16 = 8;

; --- The diagram and the note ----------------------------------------------------------------
pub const SAY_FLOW_TITLE : str = "on_comb as a circuit";
pub const SAY_FLOW_STEPS : [3]str = ["Inputs a and b: 8 bits each", "on_comb adds them", "Output result: 8 bits"];
pub const K_FLOW_STEPS : u8 = 3;
pub const SAY_NOTE : str = "Lines are what t27_compiler.wasm wrote for the verilog backend; no simulator ran here.";

test the_cells_fill_whole_rows {
    assert K_TABLE_ROWS * K_TABLE_COLS == K_TABLE_CELLS;
}

test the_table_has_a_body {
    assert K_TABLE_ROWS > 0;
    assert K_TABLE_COLS > 0;
}

test the_diagram_has_every_step {
    assert K_FLOW_STEPS == 3;
    assert K_FLOW_STEPS > 1;
}