tri fpga-rxer

RX_ER pulses injected at exact nibble positions of a ping -- preamble, mid-frame, IP header -- and the frame state each pulse leaves behind, RTL vs model.

tri fpga-rxer

tmp $ tri fpga-rxer                                                                                     
control: ping then ARP, no injection: the injector must not disturb the bench                           
  PASS rtl   TB model_errors=0 mdio_frames=50 mdio_x=0 tx_frames=2 uart_framing=0 lines=2 | rx=2 fe=0 ce
=0 aq=1 ar=1 eq=1 er=1                                                                                  
er_in_ip_header: RX_ER on data nibble 60 of the ping (IP destination, first byte): the frame ends there,
 30 bytes, below 64: fe; the tail starts with nibble C and is skipped                                   
  PASS rtl   TB model_errors=0 mdio_frames=50 mdio_x=0 tx_frames=1 uart_framing=0 lines=2 | rx=2 fe=1 ce
=0 aq=1 ar=1 eq=0 er=0                                                                                  
er_in_preamble: RX_ER on preamble nibble 5 of the ping: R_PRE clears r_5, the next 5s set it again, the 
SFD starts the frame: answered as if no error (802.3 22.2.2.5 would drop it)                            
  PASS rtl   TB model_errors=0 mdio_frames=50 mdio_x=0 tx_frames=2 uart_framing=0 lines=2 | rx=2 fe=0 ce
=0 aq=1 ar=1 eq=1 er=1                                                                                  
er_then_false_sfd: RX_ER on data nibble 67 of a frame whose payload has 55 D5 next: the frame ends (34 b
ytes: fe), the tail 5 5 5 D starts a second frame (84 bytes, FCS of the whole: fe). One errored frame co
unts rx 2, fe 2. Then the ARP is answered                                                               
  PASS rtl   TB model_errors=0 mdio_frames=50 mdio_x=0 tx_frames=1 uart_framing=0 lines=2 | rx=3 fe=2 ce
=0 aq=1 ar=1 eq=0 er=0                                                                                  
false_carrier: four nibbles of false carrier (DV 0, ER 1, RXD E) 40 nibbles after the ping: R_PRE sees E
, goes to R_SKIP until the falling sample drops: no counter, both answered                              
  PASS rtl   TB model_errors=0 mdio_frames=50 mdio_x=0 tx_frames=2 uart_framing=0 lines=2 | rx=2 fe=0 ce
=0 aq=1 ar=1 eq=1 er=1                                                                                  
5/5 checks as pre-registered; logs in /tmp/e3rxer/                                                      
tmp $

recorded 2026-10-07 20:12 UTCreal 20.1 sshown 4.4 sexit codes 0

$ tri fpga-rxer

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.

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