t27c gen-verilog on uart.t27 -- spec to RTL

The compiler lowers the UART spec to synthesizable Verilog: the TRINITY banner, the module port list and the datapath as wires.

t27c gen-verilog specs/fpga/uart.t27

    // `$print` cell and nextpnr has no BEL to place one. They are carried by                           
    // `gen-verilog-for-simulation`, which lowers every declaration below.                              
    //                                                                                                  
    // test      uart_initially_idle                                                                    
    // test      uart_tx_ready_initially                                                                
    // test      uart_rx_not_valid_initially                                                            
    // test      uart_tx_send_returns_true_when_ready                                                   
    // test      uart_tx_send_returns_false_when_busy                                                   
    // test      uart_reset_clears_status                                                               
    // test      uart_reset_restores_tx_ready                                                           
    // test      uart_configure_changes_baud_divisor                                                    
    // test      uart_configure_parity_enable                                                           
    // test      uart_bit_period_calc                                                                   
    // test      uart_constants                                                                         
    // test      uart_tx_send_updates_state                                                             
    // test      uart_rx_read_clears_valid                                                              
    // test      uart_reset_clears_rx_error                                                             
    // test      uart_reset_clears_bit_counter                                                          
    // test      uart_statement_body_with_given                                                         
    // invariant uart_status_valid                                                                      
    // invariant uart_tx_ready_inverse_tx_busy                                                          
    // bench     uart_tx_ready_latency                                                                  
    // bench     uart_rx_ready_latency                                                                  
    // bench     uart_reset_latency                                                                     
    // -------------------------------------------------------                                          

endmodule                                                                                               

`default_nettype wire                                                                                   
files $

recorded 2026-10-08 00:11 UTCreal 3.3 sshown 3.3 sexit codes 0

$ t27c gen-verilog specs/fpga/uart.t27

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.

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