t27c gen-verilog on uart_tb.t27 -- the testbench as RTL
The UART testbench spec lowered to Verilog: what a bench looks like when the compiler emits it.
t27c gen-verilog specs/fpga/testbench/uart_tb.t27
// `$print` cell and nextpnr has no BEL to place one. They are carried by
// `gen-verilog-for-simulation`, which lowers every declaration below.
//
// test uart_tb_tx_idle_high
// test uart_tb_rx_idle_high
// test uart_tb_test_data_patterns
// test uart_tb_clk_period_valid
// test uart_tb_sim_timeout_valid
// test uart_tb_counters_start_zero
// test uart_tb_all_test_data_distinct
// invariant tb_clk_period_correct
// invariant tb_timescale_defined
// invariant tb_timeout_defined
// invariant tb_test_data_defined
// invariant tb_baud_divisor_matches_uart
// invariant tb_counter_bounds
// invariant tb_sim_cycle_increments
// invariant tb_wait_cycles_increments_correctly
// invariant tb_initially_reset
// invariant tb_tx_line_idle_high
// invariant tb_timeout_prevents_infinite_loop
// bench tb_full_simulation_time
// bench tb_tx_byte_cycles
// bench tb_rx_byte_cycles
// -------------------------------------------------------
endmodule
`default_nettype wire
files $ recorded 2026-10-08 00:15 UTC real 3.8 s shown 3.8 s exit codes 0
$ t27c gen-verilog specs/fpga/testbench/uart_tb.t27
Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.
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