t27c gen-verilog on top_level.t27 -- spec to RTL

The whole design in one spec lowered to synthesizable Verilog: clocks, resets and bus wiring as the compiler emits them.

t27c gen-verilog specs/fpga/top_level.t27

    // test      system_initially_ready                                                                 
    // test      system_initially_not_busy                                                              
    // test      system_initially_no_error                                                              
    // test      system_reset_clears_state                                                              
    // test      start_processing_sets_busy                                                             
    // test      stop_processing_clears_busy                                                            
    // test      set_error_clears_busy                                                                  
    // test      get_mac_result_after_set                                                               
    // test      get_uart_data_after_set                                                                
    // test      mac_result_clears_processing                                                           
    // test      constants_clk_freq                                                                     
    // test      command_constants                                                                      
    // test      system_reset_clears_mac_result                                                         
    // test      system_reset_clears_uart_data                                                          
    // test      clear_error_does_not_affect_ready                                                      
    // test      start_processing_requires_ready                                                        
    // test      set_mac_result_negative                                                                
    // test      set_uart_data_boundary                                                                 
    // test      system_init_resets_state                                                               
    // invariant system_ready_when_not_processing                                                       
    // invariant system_error_implies_not_busy                                                          
    // invariant system_ready_implies_mac_uart_ready                                                    
    // bench     system_ready_latency                                                                   
    // bench     system_reset_latency                                                                   
    // -------------------------------------------------------                                          

endmodule                                                                                               

`default_nettype wire                                                                                   
files $

recorded 2026-10-08 00:12 UTCreal 3.5 sshown 3.5 sexit codes 0

$ t27c gen-verilog specs/fpga/top_level.t27

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.

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