t27c gen-verilog on top_tb.t27 -- the top bench
The top-level testbench spec lowered to Verilog: the whole design under one bench.
t27c gen-verilog specs/fpga/testbench/top_tb.t27
print("STATUS: SOME TESTS FAILED");
end
end
endtask
// -------------------------------------------------------
// NOT LOWERED BY THIS BACKEND
//
// `gen-verilog` emits synthesizable RTL. A test, an invariant and a
// bench are simulation constructs -- yosys turns each `$display` into a
// `$print` cell and nextpnr has no BEL to place one. They are carried by
// `gen-verilog-for-simulation`, which lowers every declaration below.
//
// test top_tb_reset_sequence
// test top_tb_ping_pong_cmd
// test top_tb_led_init_state
// test top_tb_spi_cs_active_low
// test top_tb_mac_interface_signals
// test top_tb_sim_timeout_reasonable
// invariant tb_clk_period_correct
// invariant tb_timescale_defined
// invariant tb_sim_timeout_defined
// invariant tb_counter_bounds
// invariant tb_sim_cycle_increments
// bench tb_full_simulation_time
// -------------------------------------------------------
endmodule
`default_nettype wire
files $ recorded 2026-10-08 00:16 UTC real 3.8 s shown 3.8 s exit codes 0
$ t27c gen-verilog specs/fpga/testbench/top_tb.t27
Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.
Trinity S³AI
