t27c gen-verilog on spi.t27 -- spec to RTL

The compiler lowers the SPI spec to synthesizable Verilog: the TRINITY banner, the module port list and the datapath as wires.

t27c gen-verilog specs/fpga/spi.t27

    // test      spi_initially_not_busy                                                                 
    // test      spi_transfer_when_ready                                                                
    // test      spi_transfer_when_busy                                                                 
    // test      spi_cs_idle_high                                                                       
    // test      spi_sck_idle_low                                                                       
    // test      spi_max_data_width_32                                                                  
    // test      spi_prescaler_range                                                                    
    // test      spi_cs_delays_defined                                                                  
    // invariant spi_mode_0_constant                                                                    
    // invariant spi_states_valid                                                                       
    // invariant spi_tx_states_valid                                                                    
    // invariant spi_prescaler_divides_clock                                                            
    // invariant spi_data_width_bounds                                                                  
    // invariant spi_busy_implies_cs_asserted                                                           
    // invariant spi_busy_only_in_transfer                                                              
    // invariant spi_sck_alternates                                                                     
    // invariant spi_cs_deasserted_after_transfer                                                       
    // invariant spi_rx_data_masked                                                                     
    // invariant spi_bit_count_reset_after_transfer                                                     
    // invariant spi_cs_delay_counters_reset                                                            
    // bench     spi_transfer_latency                                                                   
    // bench     spi_sck_max_frequency                                                                  
    // bench     spi_cs_assertion_time                                                                  
    // bench     spi_prescaler_change_latency                                                           
    // -------------------------------------------------------                                          

endmodule                                                                                               

`default_nettype wire                                                                                   
files $

recorded 2026-10-08 00:12 UTCreal 3.3 sshown 3.3 sexit codes 0

$ t27c gen-verilog specs/fpga/spi.t27

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.

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