t27c gen-verilog on spi_tb.t27 -- the testbench as RTL
The SPI testbench spec lowered to Verilog: what a bench looks like when the compiler emits it.
t27c gen-verilog specs/fpga/testbench/spi_tb.t27
on_comb = spi_transfer(tx_data);
__t27_ret = 1'b1;
end
endfunction
assign result = on_comb(tx_data);
// -------------------------------------------------------
// NOT LOWERED BY THIS BACKEND
//
// `gen-verilog` emits synthesizable RTL. A test, an invariant and a
// bench are simulation constructs -- yosys turns each `$display` into a
// `$print` cell and nextpnr has no BEL to place one. They are carried by
// `gen-verilog-for-simulation`, which lowers every declaration below.
//
// test test_idle_state
// test test_single_transfer
// test test_cs_assert_during_transfer
// test test_consecutive_transfers
// test test_full_duplex
// test test_zero_data_transfer
// test test_max_data_transfer
// invariant clk_div_positive
// invariant cs_high_when_idle
// bench bench_spi_throughput
// -------------------------------------------------------
endmodule
`default_nettype wire
files $ recorded 2026-10-08 00:23 UTC real 3.8 s shown 3.8 s exit codes 0
$ t27c gen-verilog specs/fpga/testbench/spi_tb.t27
Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.
Trinity S³AI
