t27c gen-verilog on memory_tb.t27 -- the testbench as RTL
The memory testbench spec lowered to Verilog: what a bench looks like when the compiler emits it.
t27c gen-verilog specs/fpga/testbench/memory_tb.t27
__t27_ret = 1'b1;
end
endfunction
assign result = on_comb(addr);
// -------------------------------------------------------
// NOT LOWERED BY THIS BACKEND
//
// `gen-verilog` emits synthesizable RTL. A test, an invariant and a
// bench are simulation constructs -- yosys turns each `$display` into a
// `$print` cell and nextpnr has no BEL to place one. They are carried by
// `gen-verilog-for-simulation`, which lowers every declaration below.
//
// test test_reset_clears
// test test_write_read_single
// test test_write_read_multiple
// test test_overwrite
// test test_all_zero_bits
// test test_all_one_bits
// test test_byte_addresses
// test test_tick_toggles_clock
// test test_on_comb_returns_mem_read
// invariant mem_size_positive
// bench bench_memory_bandwidth
// -------------------------------------------------------
endmodule
`default_nettype wire
files $ recorded 2026-10-08 00:16 UTC real 3.9 s shown 3.9 s exit codes 0
$ t27c gen-verilog specs/fpga/testbench/memory_tb.t27
Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.
Trinity S³AI
