t27c gen-verilog on integration_tb.t27 -- the integration bench
The integration testbench spec lowered to Verilog: every bus of the design in one bench.
t27c gen-verilog specs/fpga/testbench/integration_tb.t27
reg __t27_ret;
__t27_ret = 1'b0;
check_all_idle = ((((!mac_busy && uart_tx_ready) && spi_done) && mem_ready) && !bridge_busy)
;
__t27_ret = 1'b1;
end
endfunction
// -------------------------------------------------------
// NOT LOWERED BY THIS BACKEND
//
// `gen-verilog` emits synthesizable RTL. A test, an invariant and a
// bench are simulation constructs -- yosys turns each `$display` into a
// `$print` cell and nextpnr has no BEL to place one. They are carried by
// `gen-verilog-for-simulation`, which lowers every declaration below.
//
// test test_reset_all_modules
// test test_module_count
// test test_mac_uart_pipeline
// test test_spi_memory_pipeline
// test test_full_pipeline
// test test_stress_pipeline
// test test_tick_function
// invariant num_modules_positive
// bench bench_integration_throughput
// -------------------------------------------------------
endmodule
`default_nettype wire
files $ recorded 2026-10-08 00:16 UTC real 4.2 s shown 4.2 s exit codes 0
$ t27c gen-verilog specs/fpga/testbench/integration_tb.t27
Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.
Trinity S³AI
