t27c gen-verilog on bridge.t27 -- spec to RTL

The bus bridge spec lowered to synthesizable Verilog: both sides of the crossing as generated wires.

t27c gen-verilog specs/fpga/bridge.t27

    // test      bridge_spi_enabled_by_default                                                          
    // test      bridge_parse_header_requires_2_bytes                                                   
    // test      bridge_config_enables_spi                                                              
    // test      bridge_config_enables_mac                                                              
    // test      bridge_config_disables_spi                                                             
    // test      bridge_mac_opcodes_defined                                                             
    // test      bridge_mac_unit_count                                                                  
    // test      bridge_mac_handler_disabled_when_mac_off                                               
    // test      bridge_mac_handler_rejects_insufficient_data                                           
    // test      bridge_mac_handler_rejects_invalid_unit                                                
    // invariant bridge_states_valid                                                                    
    // invariant bridge_rx_tail_never_exceeds_head                                                      
    // invariant bridge_tx_tail_never_exceeds_head                                                      
    // invariant bridge_rx_available_bounds                                                             
    // invariant bridge_tx_space_bounds                                                                 
    // invariant bridge_packet_length_bounds                                                            
    // invariant bridge_timeout_counter_increments                                                      
    // invariant bridge_timeout_resets_on_expiration                                                    
    // invariant bridge_config_affects_flags                                                            
    // invariant bridge_modes_mutable                                                                   
    // bench     bridge_rx_write_latency                                                                
    // bench     bridge_tx_read_latency                                                                 
    // bench     bridge_parse_header_latency                                                            
    // bench     bridge_packet_processing_latency                                                       
    // -------------------------------------------------------                                          

endmodule                                                                                               

`default_nettype wire                                                                                   
files $

recorded 2026-10-08 00:12 UTCreal 3.4 sshown 3.4 sexit codes 0

$ t27c gen-verilog specs/fpga/bridge.t27

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.

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