t27c gen-verilog on axi4.t27 -- spec to RTL

The AXI4 spec lowered to synthesizable Verilog: the five channels' wiring and handshakes as generated wires.

t27c gen-verilog specs/fpga/axi4.t27

    // test      axi4_full_is_full                                                                      
    // test      strb_width_32bit                                                                       
    // test      strb_width_64bit                                                                       
    // test      validate_lite_ok                                                                       
    // test      validate_full_ok                                                                       
    // test      validate_empty_name                                                                    
    // test      validate_zero_addr                                                                     
    // test      validate_zero_data                                                                     
    // test      validate_non_byte_data                                                                 
    // test      validate_full_no_id                                                                    
    // test      slave_port_count_lite                                                                  
    // test      total_bus_bits_positive                                                                
    // test      lite_no_id                                                                             
    // test      full_has_id                                                                            
    // test      full_has_extras                                                                        
    // invariant addr_width_positive                                                                    
    // invariant data_width_byte_aligned                                                                
    // invariant strb_width_matches_data                                                                
    // invariant lite_has_zero_id                                                                       
    // invariant full_has_nonzero_id                                                                    
    // invariant validate_non_negative                                                                  
    // invariant total_bus_bits_positive                                                                
    // bench     validate_latency                                                                       
    // bench     port_count_latency                                                                     
    // -------------------------------------------------------                                          

endmodule                                                                                               

`default_nettype wire                                                                                   
files $

recorded 2026-10-08 00:12 UTCreal 3.3 sshown 3.3 sexit codes 0

$ t27c gen-verilog specs/fpga/axi4.t27

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.

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