t27c gen-verilog on axi4_tb.t27 -- the testbench as RTL
The AXI4 testbench spec lowered to Verilog: what a bench looks like when the compiler emits it.
t27c gen-verilog specs/fpga/testbench/axi4_tb.t27
r_ready = 1'b0;
axi_read_single = data;
__t27_ret = 1'b1;
end
endfunction
// -------------------------------------------------------
// NOT LOWERED BY THIS BACKEND
//
// `gen-verilog` emits synthesizable RTL. A test, an invariant and a
// bench are simulation constructs -- yosys turns each `$display` into a
// `$print` cell and nextpnr has no BEL to place one. They are carried by
// `gen-verilog-for-simulation`, which lowers every declaration below.
//
// test test_reset_state
// test test_single_write
// test test_single_read
// test test_write_read_roundtrip
// test test_multiple_writes
// test test_aligned_address
// test test_burst_len_zero_means_single
// test test_tick_function
// invariant data_width_power_of_2
// invariant addr_width_valid
// bench bench_axi_throughput
// -------------------------------------------------------
endmodule
`default_nettype wire
files $ recorded 2026-10-08 00:16 UTC real 3.9 s shown 3.9 s exit codes 0
$ t27c gen-verilog specs/fpga/testbench/axi4_tb.t27
Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.
Trinity S³AI
