t27c gen-verilog on apb_bridge.t27 -- spec to RTL

The APB bridge spec lowered to synthesizable Verilog: port list, PSEL and PENABLE wiring, the address decode.

t27c gen-verilog specs/fpga/apb_bridge.t27

    // test      apb_bridge_creation                                                                    
    // test      apb_bridge_with_error                                                                  
    // test      strb_width_32bit                                                                       
    // test      strb_width_16bit                                                                       
    // test      addr_bits_for_1_peripheral                                                             
    // test      addr_bits_for_4_peripherals                                                            
    // test      addr_bits_for_8_peripherals                                                            
    // test      read_request                                                                           
    // test      write_request                                                                          
    // test      ok_response                                                                            
    // test      error_response                                                                         
    // test      validate_ok                                                                            
    // test      validate_empty_name                                                                    
    // test      validate_zero_addr                                                                     
    // test      validate_zero_peripherals                                                              
    // test      validate_peripheral_map_ok                                                             
    // test      validate_peripheral_map_no_name                                                        
    // test      apb_port_count_basic                                                                   
    // invariant addr_width_positive                                                                    
    // invariant data_width_byte_aligned                                                                
    // invariant strb_matches_data                                                                      
    // invariant num_peripherals_positive                                                               
    // invariant validate_non_negative                                                                  
    // bench     validate_latency                                                                       
    // -------------------------------------------------------                                          

endmodule                                                                                               

`default_nettype wire                                                                                   
files $

recorded 2026-10-08 00:12 UTCreal 3.6 sshown 3.6 sexit codes 0

$ t27c gen-verilog specs/fpga/apb_bridge.t27

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.

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