t27c gen-verilog on apb_bridge_tb.t27 -- the testbench as RTL
The APB bridge testbench spec lowered to Verilog: what a bench looks like when the compiler emits it.
t27c gen-verilog specs/fpga/testbench/apb_bridge_tb.t27
penable = 1'b0;
apb_read = data;
__t27_ret = 1'b1;
end
endfunction
// -------------------------------------------------------
// NOT LOWERED BY THIS BACKEND
//
// `gen-verilog` emits synthesizable RTL. A test, an invariant and a
// bench are simulation constructs -- yosys turns each `$display` into a
// `$print` cell and nextpnr has no BEL to place one. They are carried by
// `gen-verilog-for-simulation`, which lowers every declaration below.
//
// test test_reset_state
// test test_apb_write
// test test_apb_read
// test test_write_read_roundtrip
// test test_multiple_apb_writes
// test test_protocol_phases
// test test_tick_functionality
// test tick_function
// invariant addr_width_valid
// invariant data_width_valid
// bench bench_apb_throughput
// -------------------------------------------------------
endmodule
`default_nettype wire
files $ recorded 2026-10-08 00:16 UTC real 4.1 s shown 4.1 s exit codes 0
$ t27c gen-verilog specs/fpga/testbench/apb_bridge_tb.t27
Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.
Trinity S³AI
