t27c on reset_sync.t27 -- the reset kinds, native
t27c 0.4.0 on a laptop (macOS): 16 tests pass natively -- async assert with sync release through 2 to 4 flops, the racy async release, and what validate accepts.
t27c on reset_sync.t27 -- the reset kinds, native
files $ t27c --version
t27c 0.4.0
files $ t27c test-report specs/fpga/reset_sync.t27 --specs-dir specs
--- test report: specs/fpga/reset_sync.t27 ---
tests 16
pass 16
FAIL 0
invariants 3 proved -- comptime, so compiling IS the check
rate 100.0%
runtime asserts executed, per test (#6509; a pass with 0 is vacuous, T730):
3 the_pipe_shifts_one_flop_per_clock
4 the_pipe_carries_the_release_downstream
2 a_two_stage_release_takes_two_clocks
2 release_latency_counts_the_flops
2 async_assert_reaches_the_output_without_a_clock
2 sync_assert_waits_for_the_clock
3 async_release_follows_the_raw_wire
1 a_short_deassert_does_not_release_the_pipe
1 the_pipe_settles_completely
2 three_stages_use_the_third_flop
2 validate_accepts_a_two_stage_synchronizer
1 zero_stages_is_an_error
1 five_stages_is_an_error
1 an_unknown_kind_is_an_error
2 one_stage_is_legal_but_not_recommended
1 async_release_is_not_recommended
vacuous passes 0 of 16 (passed with 0 runtime asserts executed)
files $ recorded 2026-10-07 17:35 UTC real 8.8 s shown 8.8 s exit codes 0 0
$ t27c --version
$ t27c test-report specs/fpga/reset_sync.t27 --specs-dir specs
Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.
Trinity S³AI
