t27c debug-hir on uart.t27 -- the bus as the compiler sees it

The UART spec lowered to hardware IR: the compiler's own view of the wires, ports and state before Verilog exists.

t27c debug-hir specs/fpga/uart.t27

            value: "baud_divisor",                                                                      
        },                                                                                              
        HirAssign {                                                                                     
            target: "uart_config.parity_enable",                                                        
            value: "parity_enable",                                                                     
        },                                                                                              
        HirAssign {                                                                                     
            target: "uart_config.stop_bits",                                                            
            value: "stop_bits",                                                                         
        },                                                                                              
        HirAssign {                                                                                     
            target: "uart_config.fifo_enable",                                                          
            value: "fifo_enable",                                                                       
        },                                                                                              
    ],                                                                                                  
    always_blocks: [],                                                                                  
    instances: [],                                                                                      
    memories: [],                                                                                       
    clock_domains: [],                                                                                  
    clock_crossings: [],                                                                                
    fifos: [],                                                                                          
    bus_ports: [],                                                                                      
    apb_bridges: [],                                                                                    
    gf16_accels: [],                                                                                    
    formal_asserts: [],                                                                                 
    formal_covers: [],                                                                                  
    formal_assumes: [],                                                                                 
    formal_config: None,                                                                                
    ternary_cores: [],                                                                                  
}files $

recorded 2026-10-08 00:22 UTCreal 3.2 sshown 3.2 sexit codes 0

$ t27c debug-hir specs/fpga/uart.t27

Staged: the prompt and the typing. Real: every byte the commands printed, at the time they printed it. Any silence longer than 2 s is shown for 2 s, and the title bar says so while it happens. Edited: home directory shown as ~.

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